576 lines
12 KiB
ArmAsm
576 lines
12 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Accelerated GHASH implementation with ARMv8 PMULL instructions.
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*
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* Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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SHASH .req v0
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SHASH2 .req v1
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T1 .req v2
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T2 .req v3
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MASK .req v4
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XL .req v5
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XM .req v6
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XH .req v7
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IN1 .req v7
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k00_16 .req v8
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k32_48 .req v9
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t3 .req v10
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t4 .req v11
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t5 .req v12
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t6 .req v13
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t7 .req v14
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t8 .req v15
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t9 .req v16
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perm1 .req v17
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perm2 .req v18
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perm3 .req v19
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sh1 .req v20
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sh2 .req v21
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sh3 .req v22
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sh4 .req v23
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ss1 .req v24
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ss2 .req v25
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ss3 .req v26
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ss4 .req v27
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XL2 .req v8
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XM2 .req v9
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XH2 .req v10
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XL3 .req v11
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XM3 .req v12
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XH3 .req v13
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TT3 .req v14
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TT4 .req v15
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HH .req v16
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HH3 .req v17
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HH4 .req v18
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HH34 .req v19
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.text
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.arch armv8-a+crypto
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.macro __pmull_p64, rd, rn, rm
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pmull \rd\().1q, \rn\().1d, \rm\().1d
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.endm
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.macro __pmull2_p64, rd, rn, rm
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pmull2 \rd\().1q, \rn\().2d, \rm\().2d
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.endm
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.macro __pmull_p8, rq, ad, bd
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ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
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ext t5.8b, \ad\().8b, \ad\().8b, #2 // A2
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ext t7.8b, \ad\().8b, \ad\().8b, #3 // A3
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__pmull_p8_\bd \rq, \ad
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.endm
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.macro __pmull2_p8, rq, ad, bd
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tbl t3.16b, {\ad\().16b}, perm1.16b // A1
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tbl t5.16b, {\ad\().16b}, perm2.16b // A2
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tbl t7.16b, {\ad\().16b}, perm3.16b // A3
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__pmull2_p8_\bd \rq, \ad
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.endm
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.macro __pmull_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH.8b, 8b,, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_SHASH2, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH2.8b, 8b,, ss1, ss2, ss3, ss4
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.endm
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.macro __pmull2_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_tail, rq, ad, bd, nb, t, b1, b2, b3, b4
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pmull\t t3.8h, t3.\nb, \bd // F = A1*B
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pmull\t t4.8h, \ad, \b1\().\nb // E = A*B1
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pmull\t t5.8h, t5.\nb, \bd // H = A2*B
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pmull\t t6.8h, \ad, \b2\().\nb // G = A*B2
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pmull\t t7.8h, t7.\nb, \bd // J = A3*B
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pmull\t t8.8h, \ad, \b3\().\nb // I = A*B3
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pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
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pmull\t \rq\().8h, \ad, \bd // D = A*B
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eor t3.16b, t3.16b, t4.16b // L = E + F
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eor t5.16b, t5.16b, t6.16b // M = G + H
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eor t7.16b, t7.16b, t8.16b // N = I + J
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uzp1 t4.2d, t3.2d, t5.2d
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uzp2 t3.2d, t3.2d, t5.2d
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uzp1 t6.2d, t7.2d, t9.2d
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uzp2 t7.2d, t7.2d, t9.2d
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// t3 = (L) (P0 + P1) << 8
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// t5 = (M) (P2 + P3) << 16
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eor t4.16b, t4.16b, t3.16b
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and t3.16b, t3.16b, k32_48.16b
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// t7 = (N) (P4 + P5) << 24
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// t9 = (K) (P6 + P7) << 32
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eor t6.16b, t6.16b, t7.16b
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and t7.16b, t7.16b, k00_16.16b
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eor t4.16b, t4.16b, t3.16b
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eor t6.16b, t6.16b, t7.16b
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zip2 t5.2d, t4.2d, t3.2d
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zip1 t3.2d, t4.2d, t3.2d
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zip2 t9.2d, t6.2d, t7.2d
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zip1 t7.2d, t6.2d, t7.2d
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ext t3.16b, t3.16b, t3.16b, #15
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ext t5.16b, t5.16b, t5.16b, #14
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ext t7.16b, t7.16b, t7.16b, #13
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ext t9.16b, t9.16b, t9.16b, #12
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eor t3.16b, t3.16b, t5.16b
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eor t7.16b, t7.16b, t9.16b
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eor \rq\().16b, \rq\().16b, t3.16b
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eor \rq\().16b, \rq\().16b, t7.16b
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.endm
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.macro __pmull_pre_p64
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add x8, x3, #16
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ld1 {HH.2d-HH4.2d}, [x8]
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trn1 SHASH2.2d, SHASH.2d, HH.2d
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trn2 T1.2d, SHASH.2d, HH.2d
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eor SHASH2.16b, SHASH2.16b, T1.16b
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trn1 HH34.2d, HH3.2d, HH4.2d
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trn2 T1.2d, HH3.2d, HH4.2d
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eor HH34.16b, HH34.16b, T1.16b
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movi MASK.16b, #0xe1
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shl MASK.2d, MASK.2d, #57
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.endm
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.macro __pmull_pre_p8
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ext SHASH2.16b, SHASH.16b, SHASH.16b, #8
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eor SHASH2.16b, SHASH2.16b, SHASH.16b
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// k00_16 := 0x0000000000000000_000000000000ffff
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// k32_48 := 0x00000000ffffffff_0000ffffffffffff
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movi k32_48.2d, #0xffffffff
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mov k32_48.h[2], k32_48.h[0]
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ushr k00_16.2d, k32_48.2d, #32
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// prepare the permutation vectors
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mov_q x5, 0x080f0e0d0c0b0a09
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movi T1.8b, #8
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dup perm1.2d, x5
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eor perm1.16b, perm1.16b, T1.16b
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ushr perm2.2d, perm1.2d, #8
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ushr perm3.2d, perm1.2d, #16
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ushr T1.2d, perm1.2d, #24
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sli perm2.2d, perm1.2d, #56
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sli perm3.2d, perm1.2d, #48
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sli T1.2d, perm1.2d, #40
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// precompute loop invariants
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tbl sh1.16b, {SHASH.16b}, perm1.16b
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tbl sh2.16b, {SHASH.16b}, perm2.16b
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tbl sh3.16b, {SHASH.16b}, perm3.16b
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tbl sh4.16b, {SHASH.16b}, T1.16b
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ext ss1.8b, SHASH2.8b, SHASH2.8b, #1
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ext ss2.8b, SHASH2.8b, SHASH2.8b, #2
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ext ss3.8b, SHASH2.8b, SHASH2.8b, #3
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ext ss4.8b, SHASH2.8b, SHASH2.8b, #4
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.endm
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//
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// PMULL (64x64->128) based reduction for CPUs that can do
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// it in a single instruction.
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//
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.macro __pmull_reduce_p64
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pmull T2.1q, XL.1d, MASK.1d
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eor XM.16b, XM.16b, T1.16b
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mov XH.d[0], XM.d[1]
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mov XM.d[1], XL.d[0]
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eor XL.16b, XM.16b, T2.16b
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ext T2.16b, XL.16b, XL.16b, #8
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pmull XL.1q, XL.1d, MASK.1d
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.endm
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//
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// Alternative reduction for CPUs that lack support for the
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// 64x64->128 PMULL instruction
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//
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.macro __pmull_reduce_p8
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eor XM.16b, XM.16b, T1.16b
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mov XL.d[1], XM.d[0]
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mov XH.d[0], XM.d[1]
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shl T1.2d, XL.2d, #57
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shl T2.2d, XL.2d, #62
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eor T2.16b, T2.16b, T1.16b
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shl T1.2d, XL.2d, #63
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eor T2.16b, T2.16b, T1.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor T2.16b, T2.16b, T1.16b
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mov XL.d[1], T2.d[0]
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mov XH.d[0], T2.d[1]
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ushr T2.2d, XL.2d, #1
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eor XH.16b, XH.16b, XL.16b
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eor XL.16b, XL.16b, T2.16b
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ushr T2.2d, T2.2d, #6
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ushr XL.2d, XL.2d, #1
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.endm
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.macro __pmull_ghash, pn
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ld1 {SHASH.2d}, [x3]
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ld1 {XL.2d}, [x1]
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__pmull_pre_\pn
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/* do the head block first, if supplied */
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cbz x4, 0f
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ld1 {T1.2d}, [x4]
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mov x4, xzr
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b 3f
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0: .ifc \pn, p64
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tbnz w0, #0, 2f // skip until #blocks is a
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tbnz w0, #1, 2f // round multiple of 4
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1: ld1 {XM3.16b-TT4.16b}, [x2], #64
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sub w0, w0, #4
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rev64 T1.16b, XM3.16b
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rev64 T2.16b, XH3.16b
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rev64 TT4.16b, TT4.16b
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rev64 TT3.16b, TT3.16b
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ext IN1.16b, TT4.16b, TT4.16b, #8
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ext XL3.16b, TT3.16b, TT3.16b, #8
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eor TT4.16b, TT4.16b, IN1.16b
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pmull2 XH2.1q, SHASH.2d, IN1.2d // a1 * b1
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pmull XL2.1q, SHASH.1d, IN1.1d // a0 * b0
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pmull XM2.1q, SHASH2.1d, TT4.1d // (a1 + a0)(b1 + b0)
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eor TT3.16b, TT3.16b, XL3.16b
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pmull2 XH3.1q, HH.2d, XL3.2d // a1 * b1
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pmull XL3.1q, HH.1d, XL3.1d // a0 * b0
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pmull2 XM3.1q, SHASH2.2d, TT3.2d // (a1 + a0)(b1 + b0)
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ext IN1.16b, T2.16b, T2.16b, #8
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eor XL2.16b, XL2.16b, XL3.16b
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eor XH2.16b, XH2.16b, XH3.16b
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eor XM2.16b, XM2.16b, XM3.16b
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eor T2.16b, T2.16b, IN1.16b
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pmull2 XH3.1q, HH3.2d, IN1.2d // a1 * b1
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pmull XL3.1q, HH3.1d, IN1.1d // a0 * b0
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pmull XM3.1q, HH34.1d, T2.1d // (a1 + a0)(b1 + b0)
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eor XL2.16b, XL2.16b, XL3.16b
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eor XH2.16b, XH2.16b, XH3.16b
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eor XM2.16b, XM2.16b, XM3.16b
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ext IN1.16b, T1.16b, T1.16b, #8
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ext TT3.16b, XL.16b, XL.16b, #8
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eor XL.16b, XL.16b, IN1.16b
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eor T1.16b, T1.16b, TT3.16b
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pmull2 XH.1q, HH4.2d, XL.2d // a1 * b1
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eor T1.16b, T1.16b, XL.16b
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pmull XL.1q, HH4.1d, XL.1d // a0 * b0
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pmull2 XM.1q, HH34.2d, T1.2d // (a1 + a0)(b1 + b0)
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eor XL.16b, XL.16b, XL2.16b
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eor XH.16b, XH.16b, XH2.16b
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eor XM.16b, XM.16b, XM2.16b
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eor T2.16b, XL.16b, XH.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor XM.16b, XM.16b, T2.16b
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__pmull_reduce_p64
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eor T2.16b, T2.16b, XH.16b
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eor XL.16b, XL.16b, T2.16b
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cbz w0, 5f
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b 1b
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.endif
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2: ld1 {T1.2d}, [x2], #16
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sub w0, w0, #1
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3: /* multiply XL by SHASH in GF(2^128) */
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CPU_LE( rev64 T1.16b, T1.16b )
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ext T2.16b, XL.16b, XL.16b, #8
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ext IN1.16b, T1.16b, T1.16b, #8
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eor T1.16b, T1.16b, T2.16b
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eor XL.16b, XL.16b, IN1.16b
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__pmull2_\pn XH, XL, SHASH // a1 * b1
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eor T1.16b, T1.16b, XL.16b
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__pmull_\pn XL, XL, SHASH // a0 * b0
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__pmull_\pn XM, T1, SHASH2 // (a1 + a0)(b1 + b0)
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4: eor T2.16b, XL.16b, XH.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor XM.16b, XM.16b, T2.16b
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__pmull_reduce_\pn
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eor T2.16b, T2.16b, XH.16b
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eor XL.16b, XL.16b, T2.16b
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cbnz w0, 0b
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5: st1 {XL.2d}, [x1]
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ret
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.endm
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/*
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* void pmull_ghash_update(int blocks, u64 dg[], const char *src,
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* struct ghash_key const *k, const char *head)
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*/
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ENTRY(pmull_ghash_update_p64)
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__pmull_ghash p64
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ENDPROC(pmull_ghash_update_p64)
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ENTRY(pmull_ghash_update_p8)
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__pmull_ghash p8
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ENDPROC(pmull_ghash_update_p8)
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KS0 .req v12
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KS1 .req v13
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INP0 .req v14
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INP1 .req v15
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.macro load_round_keys, rounds, rk
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cmp \rounds, #12
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blo 2222f /* 128 bits */
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beq 1111f /* 192 bits */
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ld1 {v17.4s-v18.4s}, [\rk], #32
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1111: ld1 {v19.4s-v20.4s}, [\rk], #32
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2222: ld1 {v21.4s-v24.4s}, [\rk], #64
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ld1 {v25.4s-v28.4s}, [\rk], #64
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ld1 {v29.4s-v31.4s}, [\rk]
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.endm
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.macro enc_round, state, key
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aese \state\().16b, \key\().16b
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aesmc \state\().16b, \state\().16b
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.endm
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.macro enc_block, state, rounds
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cmp \rounds, #12
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b.lo 2222f /* 128 bits */
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b.eq 1111f /* 192 bits */
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enc_round \state, v17
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enc_round \state, v18
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1111: enc_round \state, v19
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enc_round \state, v20
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2222: .irp key, v21, v22, v23, v24, v25, v26, v27, v28, v29
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enc_round \state, \key
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.endr
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aese \state\().16b, v30.16b
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eor \state\().16b, \state\().16b, v31.16b
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.endm
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.macro pmull_gcm_do_crypt, enc
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ld1 {SHASH.2d}, [x4], #16
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ld1 {HH.2d}, [x4]
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ld1 {XL.2d}, [x1]
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ldr x8, [x5, #8] // load lower counter
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movi MASK.16b, #0xe1
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trn1 SHASH2.2d, SHASH.2d, HH.2d
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trn2 T1.2d, SHASH.2d, HH.2d
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CPU_LE( rev x8, x8 )
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shl MASK.2d, MASK.2d, #57
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eor SHASH2.16b, SHASH2.16b, T1.16b
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.if \enc == 1
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ldr x10, [sp]
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ld1 {KS0.16b-KS1.16b}, [x10]
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.endif
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cbnz x6, 4f
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0: ld1 {INP0.16b-INP1.16b}, [x3], #32
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rev x9, x8
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add x11, x8, #1
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add x8, x8, #2
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.if \enc == 1
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eor INP0.16b, INP0.16b, KS0.16b // encrypt input
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eor INP1.16b, INP1.16b, KS1.16b
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.endif
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ld1 {KS0.8b}, [x5] // load upper counter
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rev x11, x11
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sub w0, w0, #2
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mov KS1.8b, KS0.8b
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ins KS0.d[1], x9 // set lower counter
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ins KS1.d[1], x11
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rev64 T1.16b, INP1.16b
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cmp w7, #12
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b.ge 2f // AES-192/256?
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1: enc_round KS0, v21
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ext IN1.16b, T1.16b, T1.16b, #8
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enc_round KS1, v21
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pmull2 XH2.1q, SHASH.2d, IN1.2d // a1 * b1
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enc_round KS0, v22
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eor T1.16b, T1.16b, IN1.16b
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enc_round KS1, v22
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pmull XL2.1q, SHASH.1d, IN1.1d // a0 * b0
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enc_round KS0, v23
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pmull XM2.1q, SHASH2.1d, T1.1d // (a1 + a0)(b1 + b0)
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enc_round KS1, v23
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rev64 T1.16b, INP0.16b
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ext T2.16b, XL.16b, XL.16b, #8
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enc_round KS0, v24
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ext IN1.16b, T1.16b, T1.16b, #8
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eor T1.16b, T1.16b, T2.16b
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enc_round KS1, v24
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eor XL.16b, XL.16b, IN1.16b
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enc_round KS0, v25
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eor T1.16b, T1.16b, XL.16b
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enc_round KS1, v25
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pmull2 XH.1q, HH.2d, XL.2d // a1 * b1
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enc_round KS0, v26
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pmull XL.1q, HH.1d, XL.1d // a0 * b0
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enc_round KS1, v26
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pmull2 XM.1q, SHASH2.2d, T1.2d // (a1 + a0)(b1 + b0)
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|
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enc_round KS0, v27
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eor XL.16b, XL.16b, XL2.16b
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eor XH.16b, XH.16b, XH2.16b
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enc_round KS1, v27
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eor XM.16b, XM.16b, XM2.16b
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ext T1.16b, XL.16b, XH.16b, #8
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enc_round KS0, v28
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eor T2.16b, XL.16b, XH.16b
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eor XM.16b, XM.16b, T1.16b
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|
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enc_round KS1, v28
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eor XM.16b, XM.16b, T2.16b
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|
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enc_round KS0, v29
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pmull T2.1q, XL.1d, MASK.1d
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enc_round KS1, v29
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mov XH.d[0], XM.d[1]
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mov XM.d[1], XL.d[0]
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aese KS0.16b, v30.16b
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eor XL.16b, XM.16b, T2.16b
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aese KS1.16b, v30.16b
|
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ext T2.16b, XL.16b, XL.16b, #8
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|
|
eor KS0.16b, KS0.16b, v31.16b
|
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pmull XL.1q, XL.1d, MASK.1d
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eor T2.16b, T2.16b, XH.16b
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eor KS1.16b, KS1.16b, v31.16b
|
|
eor XL.16b, XL.16b, T2.16b
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|
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.if \enc == 0
|
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eor INP0.16b, INP0.16b, KS0.16b
|
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eor INP1.16b, INP1.16b, KS1.16b
|
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.endif
|
|
|
|
st1 {INP0.16b-INP1.16b}, [x2], #32
|
|
|
|
cbnz w0, 0b
|
|
|
|
CPU_LE( rev x8, x8 )
|
|
st1 {XL.2d}, [x1]
|
|
str x8, [x5, #8] // store lower counter
|
|
|
|
.if \enc == 1
|
|
st1 {KS0.16b-KS1.16b}, [x10]
|
|
.endif
|
|
|
|
ret
|
|
|
|
2: b.eq 3f // AES-192?
|
|
enc_round KS0, v17
|
|
enc_round KS1, v17
|
|
enc_round KS0, v18
|
|
enc_round KS1, v18
|
|
3: enc_round KS0, v19
|
|
enc_round KS1, v19
|
|
enc_round KS0, v20
|
|
enc_round KS1, v20
|
|
b 1b
|
|
|
|
4: load_round_keys w7, x6
|
|
b 0b
|
|
.endm
|
|
|
|
/*
|
|
* void pmull_gcm_encrypt(int blocks, u64 dg[], u8 dst[], const u8 src[],
|
|
* struct ghash_key const *k, u8 ctr[],
|
|
* int rounds, u8 ks[])
|
|
*/
|
|
ENTRY(pmull_gcm_encrypt)
|
|
pmull_gcm_do_crypt 1
|
|
ENDPROC(pmull_gcm_encrypt)
|
|
|
|
/*
|
|
* void pmull_gcm_decrypt(int blocks, u64 dg[], u8 dst[], const u8 src[],
|
|
* struct ghash_key const *k, u8 ctr[],
|
|
* int rounds)
|
|
*/
|
|
ENTRY(pmull_gcm_decrypt)
|
|
pmull_gcm_do_crypt 0
|
|
ENDPROC(pmull_gcm_decrypt)
|
|
|
|
/*
|
|
* void pmull_gcm_encrypt_block(u8 dst[], u8 src[], u8 rk[], int rounds)
|
|
*/
|
|
ENTRY(pmull_gcm_encrypt_block)
|
|
cbz x2, 0f
|
|
load_round_keys w3, x2
|
|
0: ld1 {v0.16b}, [x1]
|
|
enc_block v0, w3
|
|
st1 {v0.16b}, [x0]
|
|
ret
|
|
ENDPROC(pmull_gcm_encrypt_block)
|