998 lines
30 KiB
C
998 lines
30 KiB
C
/* interrupt handling
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Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
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Copyright (C) 2004 Chris Kennedy <c@groovy.org>
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Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "ivtv-driver.h"
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#include "ivtv-queue.h"
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#include "ivtv-udma.h"
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#include "ivtv-irq.h"
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#include "ivtv-mailbox.h"
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#include "ivtv-vbi.h"
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#include "ivtv-yuv.h"
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#define DMA_MAGIC_COOKIE 0x000001fe
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static void ivtv_dma_dec_start(struct ivtv_stream *s);
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static const int ivtv_stream_map[] = {
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IVTV_ENC_STREAM_TYPE_MPG,
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IVTV_ENC_STREAM_TYPE_YUV,
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IVTV_ENC_STREAM_TYPE_PCM,
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IVTV_ENC_STREAM_TYPE_VBI,
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};
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static void ivtv_pio_work_handler(struct ivtv *itv)
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{
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struct ivtv_stream *s = &itv->streams[itv->cur_pio_stream];
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struct ivtv_buffer *buf;
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int i = 0;
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IVTV_DEBUG_HI_DMA("ivtv_pio_work_handler\n");
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if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS ||
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s->v4l2dev == NULL || !ivtv_use_pio(s)) {
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itv->cur_pio_stream = -1;
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/* trigger PIO complete user interrupt */
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write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44);
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return;
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}
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IVTV_DEBUG_HI_DMA("Process PIO %s\n", s->name);
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list_for_each_entry(buf, &s->q_dma.list, list) {
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u32 size = s->sg_processing[i].size & 0x3ffff;
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/* Copy the data from the card to the buffer */
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if (s->type == IVTV_DEC_STREAM_TYPE_VBI) {
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memcpy_fromio(buf->buf, itv->dec_mem + s->sg_processing[i].src - IVTV_DECODER_OFFSET, size);
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}
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else {
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memcpy_fromio(buf->buf, itv->enc_mem + s->sg_processing[i].src, size);
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}
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i++;
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if (i == s->sg_processing_size)
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break;
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}
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write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44);
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}
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void ivtv_irq_work_handler(struct work_struct *work)
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{
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struct ivtv *itv = container_of(work, struct ivtv, irq_work_queue);
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DEFINE_WAIT(wait);
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if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags))
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ivtv_pio_work_handler(itv);
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if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags))
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ivtv_vbi_work_handler(itv);
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if (test_and_clear_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags))
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ivtv_yuv_work_handler(itv);
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}
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/* Determine the required DMA size, setup enough buffers in the predma queue and
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actually copy the data from the card to the buffers in case a PIO transfer is
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required for this stream.
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*/
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static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MAX_DATA])
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{
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struct ivtv *itv = s->itv;
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struct ivtv_buffer *buf;
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u32 bytes_needed = 0;
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u32 offset, size;
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u32 UVoffset = 0, UVsize = 0;
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int skip_bufs = s->q_predma.buffers;
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int idx = s->sg_pending_size;
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int rc;
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/* sanity checks */
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if (s->v4l2dev == NULL) {
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IVTV_DEBUG_WARN("Stream %s not started\n", s->name);
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return -1;
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}
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if (!test_bit(IVTV_F_S_CLAIMED, &s->s_flags)) {
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IVTV_DEBUG_WARN("Stream %s not open\n", s->name);
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return -1;
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}
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/* determine offset, size and PTS for the various streams */
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switch (s->type) {
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case IVTV_ENC_STREAM_TYPE_MPG:
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offset = data[1];
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size = data[2];
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s->pending_pts = 0;
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break;
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case IVTV_ENC_STREAM_TYPE_YUV:
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offset = data[1];
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size = data[2];
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UVoffset = data[3];
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UVsize = data[4];
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s->pending_pts = ((u64) data[5] << 32) | data[6];
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break;
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case IVTV_ENC_STREAM_TYPE_PCM:
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offset = data[1] + 12;
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size = data[2] - 12;
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s->pending_pts = read_dec(offset - 8) |
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((u64)(read_dec(offset - 12)) << 32);
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if (itv->has_cx23415)
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offset += IVTV_DECODER_OFFSET;
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break;
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case IVTV_ENC_STREAM_TYPE_VBI:
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size = itv->vbi.enc_size * itv->vbi.fpi;
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offset = read_enc(itv->vbi.enc_start - 4) + 12;
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if (offset == 12) {
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IVTV_DEBUG_INFO("VBI offset == 0\n");
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return -1;
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}
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s->pending_pts = read_enc(offset - 4) | ((u64)read_enc(offset - 8) << 32);
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break;
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case IVTV_DEC_STREAM_TYPE_VBI:
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size = read_dec(itv->vbi.dec_start + 4) + 8;
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offset = read_dec(itv->vbi.dec_start) + itv->vbi.dec_start;
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s->pending_pts = 0;
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offset += IVTV_DECODER_OFFSET;
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break;
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default:
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/* shouldn't happen */
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return -1;
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}
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/* if this is the start of the DMA then fill in the magic cookie */
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if (s->sg_pending_size == 0 && ivtv_use_dma(s)) {
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if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
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s->type == IVTV_DEC_STREAM_TYPE_VBI)) {
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s->pending_backup = read_dec(offset - IVTV_DECODER_OFFSET);
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write_dec_sync(cpu_to_le32(DMA_MAGIC_COOKIE), offset - IVTV_DECODER_OFFSET);
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}
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else {
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s->pending_backup = read_enc(offset);
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write_enc_sync(cpu_to_le32(DMA_MAGIC_COOKIE), offset);
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}
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s->pending_offset = offset;
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}
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bytes_needed = size;
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if (s->type == IVTV_ENC_STREAM_TYPE_YUV) {
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/* The size for the Y samples needs to be rounded upwards to a
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multiple of the buf_size. The UV samples then start in the
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next buffer. */
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bytes_needed = s->buf_size * ((bytes_needed + s->buf_size - 1) / s->buf_size);
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bytes_needed += UVsize;
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}
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IVTV_DEBUG_HI_DMA("%s %s: 0x%08x bytes at 0x%08x\n",
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ivtv_use_pio(s) ? "PIO" : "DMA", s->name, bytes_needed, offset);
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rc = ivtv_queue_move(s, &s->q_free, &s->q_full, &s->q_predma, bytes_needed);
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if (rc < 0) { /* Insufficient buffers */
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IVTV_DEBUG_WARN("Cannot obtain %d bytes for %s data transfer\n",
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bytes_needed, s->name);
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return -1;
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}
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if (rc && !s->buffers_stolen && (s->s_flags & IVTV_F_S_APPL_IO)) {
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IVTV_WARN("All %s stream buffers are full. Dropping data.\n", s->name);
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IVTV_WARN("Cause: the application is not reading fast enough.\n");
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}
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s->buffers_stolen = rc;
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/* got the buffers, now fill in sg_pending */
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buf = list_entry(s->q_predma.list.next, struct ivtv_buffer, list);
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memset(buf->buf, 0, 128);
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list_for_each_entry(buf, &s->q_predma.list, list) {
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if (skip_bufs-- > 0)
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continue;
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s->sg_pending[idx].dst = buf->dma_handle;
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s->sg_pending[idx].src = offset;
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s->sg_pending[idx].size = s->buf_size;
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buf->bytesused = (size < s->buf_size) ? size : s->buf_size;
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buf->dma_xfer_cnt = s->dma_xfer_cnt;
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s->q_predma.bytesused += buf->bytesused;
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size -= buf->bytesused;
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offset += s->buf_size;
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/* Sync SG buffers */
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ivtv_buf_sync_for_device(s, buf);
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if (size == 0) { /* YUV */
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/* process the UV section */
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offset = UVoffset;
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size = UVsize;
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}
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idx++;
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}
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s->sg_pending_size = idx;
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return 0;
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}
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static void dma_post(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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struct ivtv_buffer *buf = NULL;
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struct list_head *p;
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u32 offset;
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u32 *u32buf;
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int x = 0;
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IVTV_DEBUG_HI_DMA("%s %s completed (%x)\n", ivtv_use_pio(s) ? "PIO" : "DMA",
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s->name, s->dma_offset);
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list_for_each(p, &s->q_dma.list) {
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buf = list_entry(p, struct ivtv_buffer, list);
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u32buf = (u32 *)buf->buf;
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/* Sync Buffer */
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ivtv_buf_sync_for_cpu(s, buf);
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if (x == 0 && ivtv_use_dma(s)) {
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offset = s->dma_last_offset;
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if (u32buf[offset / 4] != DMA_MAGIC_COOKIE)
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{
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for (offset = 0; offset < 64; offset++) {
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if (u32buf[offset] == DMA_MAGIC_COOKIE) {
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break;
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}
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}
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offset *= 4;
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if (offset == 256) {
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IVTV_DEBUG_WARN("%s: Couldn't find start of buffer within the first 256 bytes\n", s->name);
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offset = s->dma_last_offset;
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}
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if (s->dma_last_offset != offset)
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IVTV_DEBUG_WARN("%s: offset %d -> %d\n", s->name, s->dma_last_offset, offset);
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s->dma_last_offset = offset;
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}
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if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
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s->type == IVTV_DEC_STREAM_TYPE_VBI)) {
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write_dec_sync(0, s->dma_offset - IVTV_DECODER_OFFSET);
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}
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else {
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write_enc_sync(0, s->dma_offset);
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}
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if (offset) {
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buf->bytesused -= offset;
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memcpy(buf->buf, buf->buf + offset, buf->bytesused + offset);
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}
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*u32buf = cpu_to_le32(s->dma_backup);
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}
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x++;
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/* flag byteswap ABCD -> DCBA for MPG & VBI data outside irq */
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if (s->type == IVTV_ENC_STREAM_TYPE_MPG ||
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s->type == IVTV_ENC_STREAM_TYPE_VBI)
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buf->b_flags |= IVTV_F_B_NEED_BUF_SWAP;
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}
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if (buf)
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buf->bytesused += s->dma_last_offset;
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if (buf && s->type == IVTV_DEC_STREAM_TYPE_VBI) {
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list_for_each_entry(buf, &s->q_dma.list, list) {
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/* Parse and Groom VBI Data */
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s->q_dma.bytesused -= buf->bytesused;
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ivtv_process_vbi_data(itv, buf, 0, s->type);
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s->q_dma.bytesused += buf->bytesused;
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}
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if (s->id == -1) {
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ivtv_queue_move(s, &s->q_dma, NULL, &s->q_free, 0);
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return;
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}
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}
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ivtv_queue_move(s, &s->q_dma, NULL, &s->q_full, s->q_dma.bytesused);
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if (s->id != -1)
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wake_up(&s->waitq);
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}
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void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock)
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{
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struct ivtv *itv = s->itv;
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struct yuv_playback_info *yi = &itv->yuv_info;
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u8 frame = yi->draw_frame;
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struct yuv_frame_info *f = &yi->new_frame_info[frame];
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struct ivtv_buffer *buf;
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u32 y_size = 720 * ((f->src_h + 31) & ~31);
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u32 uv_offset = offset + IVTV_YUV_BUFFER_UV_OFFSET;
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int y_done = 0;
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int bytes_written = 0;
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unsigned long flags = 0;
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int idx = 0;
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IVTV_DEBUG_HI_DMA("DEC PREPARE DMA %s: %08x %08x\n", s->name, s->q_predma.bytesused, offset);
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/* Insert buffer block for YUV if needed */
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if (s->type == IVTV_DEC_STREAM_TYPE_YUV && f->offset_y) {
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if (yi->blanking_dmaptr) {
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s->sg_pending[idx].src = yi->blanking_dmaptr;
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s->sg_pending[idx].dst = offset;
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s->sg_pending[idx].size = 720 * 16;
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}
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offset += 720 * 16;
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idx++;
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}
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list_for_each_entry(buf, &s->q_predma.list, list) {
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/* YUV UV Offset from Y Buffer */
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if (s->type == IVTV_DEC_STREAM_TYPE_YUV && !y_done &&
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(bytes_written + buf->bytesused) >= y_size) {
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s->sg_pending[idx].src = buf->dma_handle;
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s->sg_pending[idx].dst = offset;
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s->sg_pending[idx].size = y_size - bytes_written;
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offset = uv_offset;
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if (s->sg_pending[idx].size != buf->bytesused) {
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idx++;
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s->sg_pending[idx].src =
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buf->dma_handle + s->sg_pending[idx - 1].size;
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s->sg_pending[idx].dst = offset;
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s->sg_pending[idx].size =
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buf->bytesused - s->sg_pending[idx - 1].size;
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offset += s->sg_pending[idx].size;
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}
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y_done = 1;
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} else {
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s->sg_pending[idx].src = buf->dma_handle;
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s->sg_pending[idx].dst = offset;
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s->sg_pending[idx].size = buf->bytesused;
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offset += buf->bytesused;
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}
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bytes_written += buf->bytesused;
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/* Sync SG buffers */
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ivtv_buf_sync_for_device(s, buf);
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idx++;
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}
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s->sg_pending_size = idx;
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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if (lock)
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spin_lock_irqsave(&itv->dma_reg_lock, flags);
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if (!test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
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ivtv_dma_dec_start(s);
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}
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else {
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set_bit(IVTV_F_S_DMA_PENDING, &s->s_flags);
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}
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if (lock)
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spin_unlock_irqrestore(&itv->dma_reg_lock, flags);
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}
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static void ivtv_dma_enc_start_xfer(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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s->sg_dma->src = cpu_to_le32(s->sg_processing[s->sg_processed].src);
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s->sg_dma->dst = cpu_to_le32(s->sg_processing[s->sg_processed].dst);
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s->sg_dma->size = cpu_to_le32(s->sg_processing[s->sg_processed].size | 0x80000000);
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s->sg_processed++;
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
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}
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static void ivtv_dma_dec_start_xfer(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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s->sg_dma->src = cpu_to_le32(s->sg_processing[s->sg_processed].src);
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s->sg_dma->dst = cpu_to_le32(s->sg_processing[s->sg_processed].dst);
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s->sg_dma->size = cpu_to_le32(s->sg_processing[s->sg_processed].size | 0x80000000);
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s->sg_processed++;
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->sg_handle, IVTV_REG_DECDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER);
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}
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/* start the encoder DMA */
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static void ivtv_dma_enc_start(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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struct ivtv_stream *s_vbi = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
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int i;
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IVTV_DEBUG_HI_DMA("start %s for %s\n", ivtv_use_dma(s) ? "DMA" : "PIO", s->name);
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if (s->q_predma.bytesused)
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ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
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if (ivtv_use_dma(s))
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s->sg_pending[s->sg_pending_size - 1].size += 256;
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/* If this is an MPEG stream, and VBI data is also pending, then append the
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VBI DMA to the MPEG DMA and transfer both sets of data at once.
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VBI DMA is a second class citizen compared to MPEG and mixing them together
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will confuse the firmware (the end of a VBI DMA is seen as the end of a
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MPEG DMA, thus effectively dropping an MPEG frame). So instead we make
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sure we only use the MPEG DMA to transfer the VBI DMA if both are in
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use. This way no conflicts occur. */
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clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags);
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if (s->type == IVTV_ENC_STREAM_TYPE_MPG && s_vbi->sg_pending_size &&
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s->sg_pending_size + s_vbi->sg_pending_size <= s->buffers) {
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ivtv_queue_move(s_vbi, &s_vbi->q_predma, NULL, &s_vbi->q_dma, s_vbi->q_predma.bytesused);
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if (ivtv_use_dma(s_vbi))
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s_vbi->sg_pending[s_vbi->sg_pending_size - 1].size += 256;
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for (i = 0; i < s_vbi->sg_pending_size; i++) {
|
|
s->sg_pending[s->sg_pending_size++] = s_vbi->sg_pending[i];
|
|
}
|
|
s_vbi->dma_offset = s_vbi->pending_offset;
|
|
s_vbi->sg_pending_size = 0;
|
|
s_vbi->dma_xfer_cnt++;
|
|
set_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags);
|
|
IVTV_DEBUG_HI_DMA("include DMA for %s\n", s->name);
|
|
}
|
|
|
|
s->dma_xfer_cnt++;
|
|
memcpy(s->sg_processing, s->sg_pending, sizeof(struct ivtv_sg_element) * s->sg_pending_size);
|
|
s->sg_processing_size = s->sg_pending_size;
|
|
s->sg_pending_size = 0;
|
|
s->sg_processed = 0;
|
|
s->dma_offset = s->pending_offset;
|
|
s->dma_backup = s->pending_backup;
|
|
s->dma_pts = s->pending_pts;
|
|
|
|
if (ivtv_use_pio(s)) {
|
|
set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags);
|
|
set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
|
|
set_bit(IVTV_F_I_PIO, &itv->i_flags);
|
|
itv->cur_pio_stream = s->type;
|
|
}
|
|
else {
|
|
itv->dma_retries = 0;
|
|
ivtv_dma_enc_start_xfer(s);
|
|
set_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
itv->cur_dma_stream = s->type;
|
|
itv->dma_timer.expires = jiffies + msecs_to_jiffies(100);
|
|
add_timer(&itv->dma_timer);
|
|
}
|
|
}
|
|
|
|
static void ivtv_dma_dec_start(struct ivtv_stream *s)
|
|
{
|
|
struct ivtv *itv = s->itv;
|
|
|
|
if (s->q_predma.bytesused)
|
|
ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
|
|
s->dma_xfer_cnt++;
|
|
memcpy(s->sg_processing, s->sg_pending, sizeof(struct ivtv_sg_element) * s->sg_pending_size);
|
|
s->sg_processing_size = s->sg_pending_size;
|
|
s->sg_pending_size = 0;
|
|
s->sg_processed = 0;
|
|
|
|
IVTV_DEBUG_HI_DMA("start DMA for %s\n", s->name);
|
|
itv->dma_retries = 0;
|
|
ivtv_dma_dec_start_xfer(s);
|
|
set_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
itv->cur_dma_stream = s->type;
|
|
itv->dma_timer.expires = jiffies + msecs_to_jiffies(100);
|
|
add_timer(&itv->dma_timer);
|
|
}
|
|
|
|
static void ivtv_irq_dma_read(struct ivtv *itv)
|
|
{
|
|
struct ivtv_stream *s = NULL;
|
|
struct ivtv_buffer *buf;
|
|
int hw_stream_type = 0;
|
|
|
|
IVTV_DEBUG_HI_IRQ("DEC DMA READ\n");
|
|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0) {
|
|
del_timer(&itv->dma_timer);
|
|
return;
|
|
}
|
|
|
|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
|
|
s = &itv->streams[itv->cur_dma_stream];
|
|
ivtv_stream_sync_for_cpu(s);
|
|
|
|
if (read_reg(IVTV_REG_DMASTATUS) & 0x14) {
|
|
IVTV_DEBUG_WARN("DEC DMA ERROR %x (xfer %d of %d, retry %d)\n",
|
|
read_reg(IVTV_REG_DMASTATUS),
|
|
s->sg_processed, s->sg_processing_size, itv->dma_retries);
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
if (itv->dma_retries == 3) {
|
|
/* Too many retries, give up on this frame */
|
|
itv->dma_retries = 0;
|
|
s->sg_processed = s->sg_processing_size;
|
|
}
|
|
else {
|
|
/* Retry, starting with the first xfer segment.
|
|
Just retrying the current segment is not sufficient. */
|
|
s->sg_processed = 0;
|
|
itv->dma_retries++;
|
|
}
|
|
}
|
|
if (s->sg_processed < s->sg_processing_size) {
|
|
/* DMA next buffer */
|
|
ivtv_dma_dec_start_xfer(s);
|
|
return;
|
|
}
|
|
if (s->type == IVTV_DEC_STREAM_TYPE_YUV)
|
|
hw_stream_type = 2;
|
|
IVTV_DEBUG_HI_DMA("DEC DATA READ %s: %d\n", s->name, s->q_dma.bytesused);
|
|
|
|
/* For some reason must kick the firmware, like PIO mode,
|
|
I think this tells the firmware we are done and the size
|
|
of the xfer so it can calculate what we need next.
|
|
I think we can do this part ourselves but would have to
|
|
fully calculate xfer info ourselves and not use interrupts
|
|
*/
|
|
ivtv_vapi(itv, CX2341X_DEC_SCHED_DMA_FROM_HOST, 3, 0, s->q_dma.bytesused,
|
|
hw_stream_type);
|
|
|
|
/* Free last DMA call */
|
|
while ((buf = ivtv_dequeue(s, &s->q_dma)) != NULL) {
|
|
ivtv_buf_sync_for_cpu(s, buf);
|
|
ivtv_enqueue(s, buf, &s->q_free);
|
|
}
|
|
wake_up(&s->waitq);
|
|
}
|
|
del_timer(&itv->dma_timer);
|
|
clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
itv->cur_dma_stream = -1;
|
|
wake_up(&itv->dma_waitq);
|
|
}
|
|
|
|
static void ivtv_irq_enc_dma_complete(struct ivtv *itv)
|
|
{
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
struct ivtv_stream *s;
|
|
|
|
ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
|
|
IVTV_DEBUG_HI_IRQ("ENC DMA COMPLETE %x %d (%d)\n", data[0], data[1], itv->cur_dma_stream);
|
|
if (itv->cur_dma_stream < 0) {
|
|
del_timer(&itv->dma_timer);
|
|
return;
|
|
}
|
|
s = &itv->streams[itv->cur_dma_stream];
|
|
ivtv_stream_sync_for_cpu(s);
|
|
|
|
if (data[0] & 0x18) {
|
|
IVTV_DEBUG_WARN("ENC DMA ERROR %x (offset %08x, xfer %d of %d, retry %d)\n", data[0],
|
|
s->dma_offset, s->sg_processed, s->sg_processing_size, itv->dma_retries);
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
if (itv->dma_retries == 3) {
|
|
/* Too many retries, give up on this frame */
|
|
itv->dma_retries = 0;
|
|
s->sg_processed = s->sg_processing_size;
|
|
}
|
|
else {
|
|
/* Retry, starting with the first xfer segment.
|
|
Just retrying the current segment is not sufficient. */
|
|
s->sg_processed = 0;
|
|
itv->dma_retries++;
|
|
}
|
|
}
|
|
if (s->sg_processed < s->sg_processing_size) {
|
|
/* DMA next buffer */
|
|
ivtv_dma_enc_start_xfer(s);
|
|
return;
|
|
}
|
|
del_timer(&itv->dma_timer);
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
itv->cur_dma_stream = -1;
|
|
dma_post(s);
|
|
if (test_and_clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags)) {
|
|
s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
|
|
dma_post(s);
|
|
}
|
|
s->sg_processing_size = 0;
|
|
s->sg_processed = 0;
|
|
wake_up(&itv->dma_waitq);
|
|
}
|
|
|
|
static void ivtv_irq_enc_pio_complete(struct ivtv *itv)
|
|
{
|
|
struct ivtv_stream *s;
|
|
|
|
if (itv->cur_pio_stream < 0 || itv->cur_pio_stream >= IVTV_MAX_STREAMS) {
|
|
itv->cur_pio_stream = -1;
|
|
return;
|
|
}
|
|
s = &itv->streams[itv->cur_pio_stream];
|
|
IVTV_DEBUG_HI_IRQ("ENC PIO COMPLETE %s\n", s->name);
|
|
clear_bit(IVTV_F_I_PIO, &itv->i_flags);
|
|
itv->cur_pio_stream = -1;
|
|
dma_post(s);
|
|
if (s->type == IVTV_ENC_STREAM_TYPE_MPG)
|
|
ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 0);
|
|
else if (s->type == IVTV_ENC_STREAM_TYPE_YUV)
|
|
ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 1);
|
|
else if (s->type == IVTV_ENC_STREAM_TYPE_PCM)
|
|
ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 2);
|
|
clear_bit(IVTV_F_I_PIO, &itv->i_flags);
|
|
if (test_and_clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags)) {
|
|
s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
|
|
dma_post(s);
|
|
}
|
|
wake_up(&itv->dma_waitq);
|
|
}
|
|
|
|
static void ivtv_irq_dma_err(struct ivtv *itv)
|
|
{
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
|
|
del_timer(&itv->dma_timer);
|
|
ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
|
|
IVTV_DEBUG_WARN("DMA ERROR %08x %08x %08x %d\n", data[0], data[1],
|
|
read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) &&
|
|
itv->cur_dma_stream >= 0 && itv->cur_dma_stream < IVTV_MAX_STREAMS) {
|
|
struct ivtv_stream *s = &itv->streams[itv->cur_dma_stream];
|
|
|
|
/* retry */
|
|
if (s->type >= IVTV_DEC_STREAM_TYPE_MPG)
|
|
ivtv_dma_dec_start(s);
|
|
else
|
|
ivtv_dma_enc_start(s);
|
|
return;
|
|
}
|
|
if (test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
|
|
ivtv_udma_start(itv);
|
|
return;
|
|
}
|
|
clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
itv->cur_dma_stream = -1;
|
|
wake_up(&itv->dma_waitq);
|
|
}
|
|
|
|
static void ivtv_irq_enc_start_cap(struct ivtv *itv)
|
|
{
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
struct ivtv_stream *s;
|
|
|
|
/* Get DMA destination and size arguments from card */
|
|
ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA, data);
|
|
IVTV_DEBUG_HI_IRQ("ENC START CAP %d: %08x %08x\n", data[0], data[1], data[2]);
|
|
|
|
if (data[0] > 2 || data[1] == 0 || data[2] == 0) {
|
|
IVTV_DEBUG_WARN("Unknown input: %08x %08x %08x\n",
|
|
data[0], data[1], data[2]);
|
|
return;
|
|
}
|
|
s = &itv->streams[ivtv_stream_map[data[0]]];
|
|
if (!stream_enc_dma_append(s, data)) {
|
|
set_bit(ivtv_use_pio(s) ? IVTV_F_S_PIO_PENDING : IVTV_F_S_DMA_PENDING, &s->s_flags);
|
|
}
|
|
}
|
|
|
|
static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
|
|
{
|
|
struct ivtv_stream *s_mpg = &itv->streams[IVTV_ENC_STREAM_TYPE_MPG];
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
struct ivtv_stream *s;
|
|
|
|
IVTV_DEBUG_HI_IRQ("ENC START VBI CAP\n");
|
|
s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
|
|
|
|
/* If more than two VBI buffers are pending, then
|
|
clear the old ones and start with this new one.
|
|
This can happen during transition stages when MPEG capturing is
|
|
started, but the first interrupts haven't arrived yet. During
|
|
that period VBI requests can accumulate without being able to
|
|
DMA the data. Since at most four VBI DMA buffers are available,
|
|
we just drop the old requests when there are already three
|
|
requests queued. */
|
|
if (s->sg_pending_size > 2) {
|
|
struct ivtv_buffer *buf;
|
|
list_for_each_entry(buf, &s->q_predma.list, list)
|
|
ivtv_buf_sync_for_cpu(s, buf);
|
|
ivtv_queue_move(s, &s->q_predma, NULL, &s->q_free, 0);
|
|
s->sg_pending_size = 0;
|
|
}
|
|
/* if we can append the data, and the MPEG stream isn't capturing,
|
|
then start a DMA request for just the VBI data. */
|
|
if (!stream_enc_dma_append(s, data) &&
|
|
!test_bit(IVTV_F_S_STREAMING, &s_mpg->s_flags)) {
|
|
set_bit(ivtv_use_pio(s) ? IVTV_F_S_PIO_PENDING : IVTV_F_S_DMA_PENDING, &s->s_flags);
|
|
}
|
|
}
|
|
|
|
static void ivtv_irq_dec_vbi_reinsert(struct ivtv *itv)
|
|
{
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
struct ivtv_stream *s = &itv->streams[IVTV_DEC_STREAM_TYPE_VBI];
|
|
|
|
IVTV_DEBUG_HI_IRQ("DEC VBI REINSERT\n");
|
|
if (test_bit(IVTV_F_S_CLAIMED, &s->s_flags) &&
|
|
!stream_enc_dma_append(s, data)) {
|
|
set_bit(IVTV_F_S_PIO_PENDING, &s->s_flags);
|
|
}
|
|
}
|
|
|
|
static void ivtv_irq_dec_data_req(struct ivtv *itv)
|
|
{
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
struct ivtv_stream *s;
|
|
|
|
/* YUV or MPG */
|
|
ivtv_api_get_data(&itv->dec_mbox, IVTV_MBOX_DMA, data);
|
|
|
|
if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
|
|
itv->dma_data_req_size =
|
|
1080 * ((itv->yuv_info.v4l2_src_h + 31) & ~31);
|
|
itv->dma_data_req_offset = data[1];
|
|
if (atomic_read(&itv->yuv_info.next_dma_frame) >= 0)
|
|
ivtv_yuv_frame_complete(itv);
|
|
s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
|
|
}
|
|
else {
|
|
itv->dma_data_req_size = data[2] >= 0x10000 ? 0x10000 : data[2];
|
|
itv->dma_data_req_offset = data[1];
|
|
s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
|
|
}
|
|
IVTV_DEBUG_HI_IRQ("DEC DATA REQ %s: %d %08x %u\n", s->name, s->q_full.bytesused,
|
|
itv->dma_data_req_offset, itv->dma_data_req_size);
|
|
if (itv->dma_data_req_size == 0 || s->q_full.bytesused < itv->dma_data_req_size) {
|
|
set_bit(IVTV_F_S_NEEDS_DATA, &s->s_flags);
|
|
}
|
|
else {
|
|
if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags))
|
|
ivtv_yuv_setup_stream_frame(itv);
|
|
clear_bit(IVTV_F_S_NEEDS_DATA, &s->s_flags);
|
|
ivtv_queue_move(s, &s->q_full, NULL, &s->q_predma, itv->dma_data_req_size);
|
|
ivtv_dma_stream_dec_prepare(s, itv->dma_data_req_offset + IVTV_DECODER_OFFSET, 0);
|
|
}
|
|
}
|
|
|
|
static void ivtv_irq_vsync(struct ivtv *itv)
|
|
{
|
|
/* The vsync interrupt is unusual in that it won't clear until
|
|
* the end of the first line for the current field, at which
|
|
* point it clears itself. This can result in repeated vsync
|
|
* interrupts, or a missed vsync. Read some of the registers
|
|
* to determine the line being displayed and ensure we handle
|
|
* one vsync per frame.
|
|
*/
|
|
unsigned int frame = read_reg(0x28c0) & 1;
|
|
struct yuv_playback_info *yi = &itv->yuv_info;
|
|
int last_dma_frame = atomic_read(&itv->yuv_info.next_dma_frame);
|
|
struct yuv_frame_info *f = &yi->new_frame_info[last_dma_frame];
|
|
|
|
if (0) IVTV_DEBUG_IRQ("DEC VSYNC\n");
|
|
|
|
if (((frame ^ f->sync_field) == 0 &&
|
|
((itv->last_vsync_field & 1) ^ f->sync_field)) ||
|
|
(frame != (itv->last_vsync_field & 1) && !f->interlaced)) {
|
|
int next_dma_frame = last_dma_frame;
|
|
|
|
if (!(f->interlaced && f->delay && yi->fields_lapsed < 1)) {
|
|
if (next_dma_frame >= 0 && next_dma_frame != atomic_read(&yi->next_fill_frame)) {
|
|
write_reg(yuv_offset[next_dma_frame] >> 4, 0x82c);
|
|
write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x830);
|
|
write_reg(yuv_offset[next_dma_frame] >> 4, 0x834);
|
|
write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x838);
|
|
next_dma_frame = (next_dma_frame + 1) % IVTV_YUV_BUFFERS;
|
|
atomic_set(&yi->next_dma_frame, next_dma_frame);
|
|
yi->fields_lapsed = -1;
|
|
}
|
|
}
|
|
}
|
|
if (frame != (itv->last_vsync_field & 1)) {
|
|
struct ivtv_stream *s = ivtv_get_output_stream(itv);
|
|
|
|
itv->last_vsync_field += 1;
|
|
if (frame == 0) {
|
|
clear_bit(IVTV_F_I_VALID_DEC_TIMINGS, &itv->i_flags);
|
|
clear_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
|
|
}
|
|
else {
|
|
set_bit(IVTV_F_I_EV_VSYNC_FIELD, &itv->i_flags);
|
|
}
|
|
if (test_bit(IVTV_F_I_EV_VSYNC_ENABLED, &itv->i_flags)) {
|
|
set_bit(IVTV_F_I_EV_VSYNC, &itv->i_flags);
|
|
wake_up(&itv->event_waitq);
|
|
}
|
|
wake_up(&itv->vsync_waitq);
|
|
if (s)
|
|
wake_up(&s->waitq);
|
|
|
|
/* Send VBI to saa7127 */
|
|
if (frame && (itv->output_mode == OUT_PASSTHROUGH ||
|
|
test_bit(IVTV_F_I_UPDATE_WSS, &itv->i_flags) ||
|
|
test_bit(IVTV_F_I_UPDATE_VPS, &itv->i_flags) ||
|
|
test_bit(IVTV_F_I_UPDATE_CC, &itv->i_flags))) {
|
|
set_bit(IVTV_F_I_WORK_HANDLER_VBI, &itv->i_flags);
|
|
set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
|
|
}
|
|
|
|
/* Check if we need to update the yuv registers */
|
|
if ((yi->yuv_forced_update || f->update) && last_dma_frame != -1) {
|
|
if (!f->update) {
|
|
last_dma_frame = (u8)(last_dma_frame - 1) % IVTV_YUV_BUFFERS;
|
|
f = &yi->new_frame_info[last_dma_frame];
|
|
}
|
|
|
|
if (f->src_w) {
|
|
yi->update_frame = last_dma_frame;
|
|
f->update = 0;
|
|
yi->yuv_forced_update = 0;
|
|
set_bit(IVTV_F_I_WORK_HANDLER_YUV, &itv->i_flags);
|
|
set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
|
|
}
|
|
}
|
|
|
|
yi->fields_lapsed++;
|
|
}
|
|
}
|
|
|
|
#define IVTV_IRQ_DMA (IVTV_IRQ_DMA_READ | IVTV_IRQ_ENC_DMA_COMPLETE | IVTV_IRQ_DMA_ERR | IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_VBI_CAP | IVTV_IRQ_DEC_DATA_REQ | IVTV_IRQ_DEC_VBI_RE_INSERT)
|
|
|
|
irqreturn_t ivtv_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct ivtv *itv = (struct ivtv *)dev_id;
|
|
u32 combo;
|
|
u32 stat;
|
|
int i;
|
|
u8 vsync_force = 0;
|
|
|
|
spin_lock(&itv->dma_reg_lock);
|
|
/* get contents of irq status register */
|
|
stat = read_reg(IVTV_REG_IRQSTATUS);
|
|
|
|
combo = ~itv->irqmask & stat;
|
|
|
|
/* Clear out IRQ */
|
|
if (combo) write_reg(combo, IVTV_REG_IRQSTATUS);
|
|
|
|
if (0 == combo) {
|
|
/* The vsync interrupt is unusual and clears itself. If we
|
|
* took too long, we may have missed it. Do some checks
|
|
*/
|
|
if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
|
|
/* vsync is enabled, see if we're in a new field */
|
|
if ((itv->last_vsync_field & 1) != (read_reg(0x28c0) & 1)) {
|
|
/* New field, looks like we missed it */
|
|
IVTV_DEBUG_YUV("VSync interrupt missed %d\n",read_reg(0x28c0)>>16);
|
|
vsync_force = 1;
|
|
}
|
|
}
|
|
|
|
if (!vsync_force) {
|
|
/* No Vsync expected, wasn't for us */
|
|
spin_unlock(&itv->dma_reg_lock);
|
|
return IRQ_NONE;
|
|
}
|
|
}
|
|
|
|
/* Exclude interrupts noted below from the output, otherwise the log is flooded with
|
|
these messages */
|
|
if (combo & ~0xff6d0400)
|
|
IVTV_DEBUG_HI_IRQ("======= valid IRQ bits: 0x%08x ======\n", combo);
|
|
|
|
if (combo & IVTV_IRQ_DEC_DMA_COMPLETE) {
|
|
IVTV_DEBUG_HI_IRQ("DEC DMA COMPLETE\n");
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_DMA_READ) {
|
|
ivtv_irq_dma_read(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_ENC_DMA_COMPLETE) {
|
|
ivtv_irq_enc_dma_complete(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_ENC_PIO_COMPLETE) {
|
|
ivtv_irq_enc_pio_complete(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_DMA_ERR) {
|
|
ivtv_irq_dma_err(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_ENC_START_CAP) {
|
|
ivtv_irq_enc_start_cap(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_ENC_VBI_CAP) {
|
|
ivtv_irq_enc_vbi_cap(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_DEC_VBI_RE_INSERT) {
|
|
ivtv_irq_dec_vbi_reinsert(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_ENC_EOS) {
|
|
IVTV_DEBUG_IRQ("ENC EOS\n");
|
|
set_bit(IVTV_F_I_EOS, &itv->i_flags);
|
|
wake_up(&itv->eos_waitq);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_DEC_DATA_REQ) {
|
|
ivtv_irq_dec_data_req(itv);
|
|
}
|
|
|
|
/* Decoder Vertical Sync - We can't rely on 'combo', so check if vsync enabled */
|
|
if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) {
|
|
ivtv_irq_vsync(itv);
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_ENC_VIM_RST) {
|
|
IVTV_DEBUG_IRQ("VIM RST\n");
|
|
/*ivtv_vapi(itv, CX2341X_ENC_REFRESH_INPUT, 0); */
|
|
}
|
|
|
|
if (combo & IVTV_IRQ_DEC_AUD_MODE_CHG) {
|
|
IVTV_DEBUG_INFO("Stereo mode changed\n");
|
|
}
|
|
|
|
if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_DMA, &itv->i_flags)) {
|
|
itv->irq_rr_idx++;
|
|
for (i = 0; i < IVTV_MAX_STREAMS; i++) {
|
|
int idx = (i + itv->irq_rr_idx) % IVTV_MAX_STREAMS;
|
|
struct ivtv_stream *s = &itv->streams[idx];
|
|
|
|
if (!test_and_clear_bit(IVTV_F_S_DMA_PENDING, &s->s_flags))
|
|
continue;
|
|
if (s->type >= IVTV_DEC_STREAM_TYPE_MPG)
|
|
ivtv_dma_dec_start(s);
|
|
else
|
|
ivtv_dma_enc_start(s);
|
|
break;
|
|
}
|
|
if (i == IVTV_MAX_STREAMS && test_and_clear_bit(IVTV_F_I_UDMA_PENDING, &itv->i_flags)) {
|
|
ivtv_udma_start(itv);
|
|
}
|
|
}
|
|
|
|
if ((combo & IVTV_IRQ_DMA) && !test_bit(IVTV_F_I_PIO, &itv->i_flags)) {
|
|
itv->irq_rr_idx++;
|
|
for (i = 0; i < IVTV_MAX_STREAMS; i++) {
|
|
int idx = (i + itv->irq_rr_idx) % IVTV_MAX_STREAMS;
|
|
struct ivtv_stream *s = &itv->streams[idx];
|
|
|
|
if (!test_and_clear_bit(IVTV_F_S_PIO_PENDING, &s->s_flags))
|
|
continue;
|
|
if (s->type == IVTV_DEC_STREAM_TYPE_VBI || s->type < IVTV_DEC_STREAM_TYPE_MPG)
|
|
ivtv_dma_enc_start(s);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (test_and_clear_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags)) {
|
|
queue_work(itv->irq_work_queues, &itv->irq_work_queue);
|
|
}
|
|
|
|
spin_unlock(&itv->dma_reg_lock);
|
|
|
|
/* If we've just handled a 'forced' vsync, it's safest to say it
|
|
* wasn't ours. Another device may have triggered it at just
|
|
* the right time.
|
|
*/
|
|
return vsync_force ? IRQ_NONE : IRQ_HANDLED;
|
|
}
|
|
|
|
void ivtv_unfinished_dma(unsigned long arg)
|
|
{
|
|
struct ivtv *itv = (struct ivtv *)arg;
|
|
|
|
if (!test_bit(IVTV_F_I_DMA, &itv->i_flags))
|
|
return;
|
|
IVTV_ERR("DMA TIMEOUT %08x %d\n", read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
|
|
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
itv->cur_dma_stream = -1;
|
|
wake_up(&itv->dma_waitq);
|
|
}
|