1005 lines
25 KiB
C
1005 lines
25 KiB
C
#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/timer.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/cpufreq.h>
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#include <linux/dmi.h>
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#include <linux/delay.h>
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#include <linux/clocksource.h>
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#include <linux/percpu.h>
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#include <linux/timex.h>
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#include <asm/hpet.h>
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#include <asm/timer.h>
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#include <asm/vgtod.h>
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#include <asm/time.h>
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#include <asm/delay.h>
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#include <asm/hypervisor.h>
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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EXPORT_SYMBOL(cpu_khz);
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unsigned int __read_mostly tsc_khz;
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EXPORT_SYMBOL(tsc_khz);
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/*
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* TSC can be unstable due to cpufreq or due to unsynced TSCs
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*/
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static int __read_mostly tsc_unstable;
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/* native_sched_clock() is called before tsc_init(), so
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we must start with the TSC soft disabled to prevent
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erroneous rdtsc usage on !cpu_has_tsc processors */
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static int __read_mostly tsc_disabled = -1;
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static int tsc_clocksource_reliable;
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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u64 native_sched_clock(void)
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{
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u64 this_offset;
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/*
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* Fall back to jiffies if there's no TSC available:
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* ( But note that we still use it if the TSC is marked
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* unstable. We do this because unlike Time Of Day,
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* the scheduler clock tolerates small errors and it's
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* very important for it to be as fast as the platform
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* can achieve it. )
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*/
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if (unlikely(tsc_disabled)) {
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/* No locking but a rare wrong value is not a big deal: */
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return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
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}
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/* read the Time Stamp Counter: */
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rdtscll(this_offset);
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/* return the value in ns */
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return __cycles_2_ns(this_offset);
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}
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/* We need to define a real function for sched_clock, to override the
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weak default version */
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#ifdef CONFIG_PARAVIRT
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unsigned long long sched_clock(void)
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{
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return paravirt_sched_clock();
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}
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#else
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unsigned long long
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sched_clock(void) __attribute__((alias("native_sched_clock")));
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#endif
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int check_tsc_unstable(void)
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{
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return tsc_unstable;
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}
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EXPORT_SYMBOL_GPL(check_tsc_unstable);
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#ifdef CONFIG_X86_TSC
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int __init notsc_setup(char *str)
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{
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printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
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"cannot disable TSC completely.\n");
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tsc_disabled = 1;
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return 1;
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}
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#else
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/*
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* disable flag for tsc. Takes effect by clearing the TSC cpu flag
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* in cpu/common.c
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*/
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int __init notsc_setup(char *str)
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{
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setup_clear_cpu_cap(X86_FEATURE_TSC);
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return 1;
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}
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#endif
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__setup("notsc", notsc_setup);
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static int __init tsc_setup(char *str)
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{
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if (!strcmp(str, "reliable"))
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tsc_clocksource_reliable = 1;
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return 1;
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}
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__setup("tsc=", tsc_setup);
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#define MAX_RETRIES 5
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#define SMI_TRESHOLD 50000
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/*
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* Read TSC and the reference counters. Take care of SMI disturbance
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*/
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static u64 tsc_read_refs(u64 *p, int hpet)
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{
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u64 t1, t2;
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int i;
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for (i = 0; i < MAX_RETRIES; i++) {
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t1 = get_cycles();
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if (hpet)
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*p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
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else
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*p = acpi_pm_read_early();
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t2 = get_cycles();
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if ((t2 - t1) < SMI_TRESHOLD)
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return t2;
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}
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return ULLONG_MAX;
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}
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/*
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* Calculate the TSC frequency from HPET reference
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*/
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static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
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{
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u64 tmp;
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if (hpet2 < hpet1)
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hpet2 += 0x100000000ULL;
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hpet2 -= hpet1;
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tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
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do_div(tmp, 1000000);
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do_div(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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/*
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* Calculate the TSC frequency from PMTimer reference
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*/
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static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
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{
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u64 tmp;
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if (!pm1 && !pm2)
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return ULONG_MAX;
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if (pm2 < pm1)
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pm2 += (u64)ACPI_PM_OVRRUN;
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pm2 -= pm1;
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tmp = pm2 * 1000000000LL;
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do_div(tmp, PMTMR_TICKS_PER_SEC);
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do_div(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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#define CAL_MS 10
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#define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
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#define CAL_PIT_LOOPS 1000
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#define CAL2_MS 50
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#define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
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#define CAL2_PIT_LOOPS 5000
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/*
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* Try to calibrate the TSC against the Programmable
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* Interrupt Timer and return the frequency of the TSC
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* in kHz.
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*
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* Return ULONG_MAX on failure to calibrate.
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*/
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static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
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{
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u64 tsc, t1, t2, delta;
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unsigned long tscmin, tscmax;
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int pitcnt;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Setup CTC channel 2* for mode 0, (interrupt on terminal
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* count mode), binary count. Set the latch register to 50ms
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* (LSB then MSB) to begin countdown.
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*/
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outb(0xb0, 0x43);
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outb(latch & 0xff, 0x42);
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outb(latch >> 8, 0x42);
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tsc = t1 = t2 = get_cycles();
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pitcnt = 0;
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tscmax = 0;
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tscmin = ULONG_MAX;
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while ((inb(0x61) & 0x20) == 0) {
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t2 = get_cycles();
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delta = t2 - tsc;
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tsc = t2;
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if ((unsigned long) delta < tscmin)
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tscmin = (unsigned int) delta;
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if ((unsigned long) delta > tscmax)
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tscmax = (unsigned int) delta;
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pitcnt++;
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}
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/*
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* Sanity checks:
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*
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* If we were not able to read the PIT more than loopmin
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* times, then we have been hit by a massive SMI
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*
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* If the maximum is 10 times larger than the minimum,
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* then we got hit by an SMI as well.
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*/
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if (pitcnt < loopmin || tscmax > 10 * tscmin)
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return ULONG_MAX;
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/* Calculate the PIT value */
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delta = t2 - t1;
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do_div(delta, ms);
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return delta;
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}
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/*
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* This reads the current MSB of the PIT counter, and
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* checks if we are running on sufficiently fast and
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* non-virtualized hardware.
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*
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* Our expectations are:
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*
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* - the PIT is running at roughly 1.19MHz
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*
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* - each IO is going to take about 1us on real hardware,
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* but we allow it to be much faster (by a factor of 10) or
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* _slightly_ slower (ie we allow up to a 2us read+counter
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* update - anything else implies a unacceptably slow CPU
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* or PIT for the fast calibration to work.
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*
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* - with 256 PIT ticks to read the value, we have 214us to
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* see the same MSB (and overhead like doing a single TSC
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* read per MSB value etc).
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*
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* - We're doing 2 reads per loop (LSB, MSB), and we expect
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* them each to take about a microsecond on real hardware.
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* So we expect a count value of around 100. But we'll be
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* generous, and accept anything over 50.
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*
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* - if the PIT is stuck, and we see *many* more reads, we
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* return early (and the next caller of pit_expect_msb()
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* then consider it a failure when they don't see the
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* next expected value).
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*
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* These expectations mean that we know that we have seen the
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* transition from one expected value to another with a fairly
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* high accuracy, and we didn't miss any events. We can thus
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* use the TSC value at the transitions to calculate a pretty
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* good value for the TSC frequencty.
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*/
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static inline int pit_verify_msb(unsigned char val)
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{
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/* Ignore LSB */
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inb(0x42);
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return inb(0x42) == val;
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}
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static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
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{
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int count;
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u64 tsc = 0;
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for (count = 0; count < 50000; count++) {
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if (!pit_verify_msb(val))
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break;
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tsc = get_cycles();
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}
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*deltap = get_cycles() - tsc;
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*tscp = tsc;
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/*
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* We require _some_ success, but the quality control
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* will be based on the error terms on the TSC values.
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*/
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return count > 5;
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}
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/*
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* How many MSB values do we want to see? We aim for
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* a maximum error rate of 500ppm (in practice the
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* real error is much smaller), but refuse to spend
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* more than 25ms on it.
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*/
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#define MAX_QUICK_PIT_MS 25
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#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
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static unsigned long quick_pit_calibrate(void)
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{
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int i;
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u64 tsc, delta;
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unsigned long d1, d2;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Counter 2, mode 0 (one-shot), binary count
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*
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* NOTE! Mode 2 decrements by two (and then the
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* output is flipped each time, giving the same
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* final output frequency as a decrement-by-one),
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* so mode 0 is much better when looking at the
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* individual counts.
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*/
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outb(0xb0, 0x43);
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/* Start at 0xffff */
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outb(0xff, 0x42);
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outb(0xff, 0x42);
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/*
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* The PIT starts counting at the next edge, so we
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* need to delay for a microsecond. The easiest way
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* to do that is to just read back the 16-bit counter
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* once from the PIT.
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*/
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pit_verify_msb(0);
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if (pit_expect_msb(0xff, &tsc, &d1)) {
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for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
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if (!pit_expect_msb(0xff-i, &delta, &d2))
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break;
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/*
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* Iterate until the error is less than 500 ppm
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*/
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delta -= tsc;
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if (d1+d2 >= delta >> 11)
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continue;
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/*
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* Check the PIT one more time to verify that
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* all TSC reads were stable wrt the PIT.
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*
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* This also guarantees serialization of the
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* last cycle read ('d2') in pit_expect_msb.
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*/
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if (!pit_verify_msb(0xfe - i))
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break;
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goto success;
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}
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}
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printk("Fast TSC calibration failed\n");
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return 0;
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success:
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/*
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* Ok, if we get here, then we've seen the
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* MSB of the PIT decrement 'i' times, and the
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* error has shrunk to less than 500 ppm.
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*
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* As a result, we can depend on there not being
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* any odd delays anywhere, and the TSC reads are
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* reliable (within the error). We also adjust the
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* delta to the middle of the error bars, just
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* because it looks nicer.
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*
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* kHz = ticks / time-in-seconds / 1000;
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* kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
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* kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
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*/
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delta += (long)(d2 - d1)/2;
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delta *= PIT_TICK_RATE;
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do_div(delta, i*256*1000);
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printk("Fast TSC calibration using PIT\n");
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return delta;
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}
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/**
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* native_calibrate_tsc - calibrate the tsc on boot
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*/
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unsigned long native_calibrate_tsc(void)
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{
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u64 tsc1, tsc2, delta, ref1, ref2;
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unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
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unsigned long flags, latch, ms, fast_calibrate;
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int hpet = is_hpet_enabled(), i, loopmin;
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local_irq_save(flags);
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fast_calibrate = quick_pit_calibrate();
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local_irq_restore(flags);
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if (fast_calibrate)
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return fast_calibrate;
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/*
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* Run 5 calibration loops to get the lowest frequency value
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* (the best estimate). We use two different calibration modes
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* here:
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*
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* 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
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* load a timeout of 50ms. We read the time right after we
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* started the timer and wait until the PIT count down reaches
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* zero. In each wait loop iteration we read the TSC and check
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* the delta to the previous read. We keep track of the min
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* and max values of that delta. The delta is mostly defined
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* by the IO time of the PIT access, so we can detect when a
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* SMI/SMM disturbance happend between the two reads. If the
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* maximum time is significantly larger than the minimum time,
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* then we discard the result and have another try.
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*
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* 2) Reference counter. If available we use the HPET or the
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* PMTIMER as a reference to check the sanity of that value.
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* We use separate TSC readouts and check inside of the
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* reference read for a SMI/SMM disturbance. We dicard
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* disturbed values here as well. We do that around the PIT
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* calibration delay loop as we have to wait for a certain
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* amount of time anyway.
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*/
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/* Preset PIT loop values */
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latch = CAL_LATCH;
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ms = CAL_MS;
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loopmin = CAL_PIT_LOOPS;
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for (i = 0; i < 3; i++) {
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unsigned long tsc_pit_khz;
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/*
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* Read the start value and the reference count of
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* hpet/pmtimer when available. Then do the PIT
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* calibration, which will take at least 50ms, and
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* read the end value.
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*/
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local_irq_save(flags);
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tsc1 = tsc_read_refs(&ref1, hpet);
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tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
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tsc2 = tsc_read_refs(&ref2, hpet);
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local_irq_restore(flags);
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/* Pick the lowest PIT TSC calibration so far */
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tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
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/* hpet or pmtimer available ? */
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if (!hpet && !ref1 && !ref2)
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continue;
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/* Check, whether the sampling was disturbed by an SMI */
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if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
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continue;
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tsc2 = (tsc2 - tsc1) * 1000000LL;
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if (hpet)
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tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
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else
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tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
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tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
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/* Check the reference deviation */
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delta = ((u64) tsc_pit_min) * 100;
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do_div(delta, tsc_ref_min);
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/*
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* If both calibration results are inside a 10% window
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* then we can be sure, that the calibration
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* succeeded. We break out of the loop right away. We
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* use the reference value, as it is more precise.
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*/
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if (delta >= 90 && delta <= 110) {
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printk(KERN_INFO
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"TSC: PIT calibration matches %s. %d loops\n",
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hpet ? "HPET" : "PMTIMER", i + 1);
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return tsc_ref_min;
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}
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/*
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* Check whether PIT failed more than once. This
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* happens in virtualized environments. We need to
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* give the virtual PC a slightly longer timeframe for
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* the HPET/PMTIMER to make the result precise.
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*/
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if (i == 1 && tsc_pit_min == ULONG_MAX) {
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latch = CAL2_LATCH;
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ms = CAL2_MS;
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loopmin = CAL2_PIT_LOOPS;
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}
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}
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/*
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* Now check the results.
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*/
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if (tsc_pit_min == ULONG_MAX) {
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/* PIT gave no useful value */
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printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
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/* We don't have an alternative source, disable TSC */
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if (!hpet && !ref1 && !ref2) {
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printk("TSC: No reference (HPET/PMTIMER) available\n");
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return 0;
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}
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|
|
/* The alternative source failed as well, disable TSC */
|
|
if (tsc_ref_min == ULONG_MAX) {
|
|
printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
|
|
"failed.\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Use the alternative source */
|
|
printk(KERN_INFO "TSC: using %s reference calibration\n",
|
|
hpet ? "HPET" : "PMTIMER");
|
|
|
|
return tsc_ref_min;
|
|
}
|
|
|
|
/* We don't have an alternative source, use the PIT calibration value */
|
|
if (!hpet && !ref1 && !ref2) {
|
|
printk(KERN_INFO "TSC: Using PIT calibration value\n");
|
|
return tsc_pit_min;
|
|
}
|
|
|
|
/* The alternative source failed, use the PIT calibration value */
|
|
if (tsc_ref_min == ULONG_MAX) {
|
|
printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
|
|
"Using PIT calibration\n");
|
|
return tsc_pit_min;
|
|
}
|
|
|
|
/*
|
|
* The calibration values differ too much. In doubt, we use
|
|
* the PIT value as we know that there are PMTIMERs around
|
|
* running at double speed. At least we let the user know:
|
|
*/
|
|
printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
|
|
hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
|
|
printk(KERN_INFO "TSC: Using PIT calibration value\n");
|
|
return tsc_pit_min;
|
|
}
|
|
|
|
int recalibrate_cpu_khz(void)
|
|
{
|
|
#ifndef CONFIG_SMP
|
|
unsigned long cpu_khz_old = cpu_khz;
|
|
|
|
if (cpu_has_tsc) {
|
|
tsc_khz = x86_platform.calibrate_tsc();
|
|
cpu_khz = tsc_khz;
|
|
cpu_data(0).loops_per_jiffy =
|
|
cpufreq_scale(cpu_data(0).loops_per_jiffy,
|
|
cpu_khz_old, cpu_khz);
|
|
return 0;
|
|
} else
|
|
return -ENODEV;
|
|
#else
|
|
return -ENODEV;
|
|
#endif
|
|
}
|
|
|
|
EXPORT_SYMBOL(recalibrate_cpu_khz);
|
|
|
|
|
|
/* Accelerators for sched_clock()
|
|
* convert from cycles(64bits) => nanoseconds (64bits)
|
|
* basic equation:
|
|
* ns = cycles / (freq / ns_per_sec)
|
|
* ns = cycles * (ns_per_sec / freq)
|
|
* ns = cycles * (10^9 / (cpu_khz * 10^3))
|
|
* ns = cycles * (10^6 / cpu_khz)
|
|
*
|
|
* Then we use scaling math (suggested by george@mvista.com) to get:
|
|
* ns = cycles * (10^6 * SC / cpu_khz) / SC
|
|
* ns = cycles * cyc2ns_scale / SC
|
|
*
|
|
* And since SC is a constant power of two, we can convert the div
|
|
* into a shift.
|
|
*
|
|
* We can use khz divisor instead of mhz to keep a better precision, since
|
|
* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
|
|
* (mathieu.desnoyers@polymtl.ca)
|
|
*
|
|
* -johnstul@us.ibm.com "math is hard, lets go shopping!"
|
|
*/
|
|
|
|
DEFINE_PER_CPU(unsigned long, cyc2ns);
|
|
DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
|
|
|
|
static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
|
|
{
|
|
unsigned long long tsc_now, ns_now, *offset;
|
|
unsigned long flags, *scale;
|
|
|
|
local_irq_save(flags);
|
|
sched_clock_idle_sleep_event();
|
|
|
|
scale = &per_cpu(cyc2ns, cpu);
|
|
offset = &per_cpu(cyc2ns_offset, cpu);
|
|
|
|
rdtscll(tsc_now);
|
|
ns_now = __cycles_2_ns(tsc_now);
|
|
|
|
if (cpu_khz) {
|
|
*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
|
|
*offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR);
|
|
}
|
|
|
|
sched_clock_idle_wakeup_event(0);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static unsigned long long cyc2ns_suspend;
|
|
|
|
void save_sched_clock_state(void)
|
|
{
|
|
if (!sched_clock_stable)
|
|
return;
|
|
|
|
cyc2ns_suspend = sched_clock();
|
|
}
|
|
|
|
/*
|
|
* Even on processors with invariant TSC, TSC gets reset in some the
|
|
* ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
|
|
* arbitrary value (still sync'd across cpu's) during resume from such sleep
|
|
* states. To cope up with this, recompute the cyc2ns_offset for each cpu so
|
|
* that sched_clock() continues from the point where it was left off during
|
|
* suspend.
|
|
*/
|
|
void restore_sched_clock_state(void)
|
|
{
|
|
unsigned long long offset;
|
|
unsigned long flags;
|
|
int cpu;
|
|
|
|
if (!sched_clock_stable)
|
|
return;
|
|
|
|
local_irq_save(flags);
|
|
|
|
__get_cpu_var(cyc2ns_offset) = 0;
|
|
offset = cyc2ns_suspend - sched_clock();
|
|
|
|
for_each_possible_cpu(cpu)
|
|
per_cpu(cyc2ns_offset, cpu) = offset;
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
|
|
* changes.
|
|
*
|
|
* RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
|
|
* not that important because current Opteron setups do not support
|
|
* scaling on SMP anyroads.
|
|
*
|
|
* Should fix up last_tsc too. Currently gettimeofday in the
|
|
* first tick after the change will be slightly wrong.
|
|
*/
|
|
|
|
static unsigned int ref_freq;
|
|
static unsigned long loops_per_jiffy_ref;
|
|
static unsigned long tsc_khz_ref;
|
|
|
|
static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
|
|
void *data)
|
|
{
|
|
struct cpufreq_freqs *freq = data;
|
|
unsigned long *lpj;
|
|
|
|
if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
|
|
return 0;
|
|
|
|
lpj = &boot_cpu_data.loops_per_jiffy;
|
|
#ifdef CONFIG_SMP
|
|
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
|
|
lpj = &cpu_data(freq->cpu).loops_per_jiffy;
|
|
#endif
|
|
|
|
if (!ref_freq) {
|
|
ref_freq = freq->old;
|
|
loops_per_jiffy_ref = *lpj;
|
|
tsc_khz_ref = tsc_khz;
|
|
}
|
|
if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
|
|
(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
|
|
(val == CPUFREQ_RESUMECHANGE)) {
|
|
*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
|
|
|
|
tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
|
|
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
|
|
mark_tsc_unstable("cpufreq changes");
|
|
}
|
|
|
|
set_cyc2ns_scale(tsc_khz, freq->cpu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block time_cpufreq_notifier_block = {
|
|
.notifier_call = time_cpufreq_notifier
|
|
};
|
|
|
|
static int __init cpufreq_tsc(void)
|
|
{
|
|
if (!cpu_has_tsc)
|
|
return 0;
|
|
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
|
|
return 0;
|
|
cpufreq_register_notifier(&time_cpufreq_notifier_block,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
return 0;
|
|
}
|
|
|
|
core_initcall(cpufreq_tsc);
|
|
|
|
#endif /* CONFIG_CPU_FREQ */
|
|
|
|
/* clocksource code */
|
|
|
|
static struct clocksource clocksource_tsc;
|
|
|
|
/*
|
|
* We compare the TSC to the cycle_last value in the clocksource
|
|
* structure to avoid a nasty time-warp. This can be observed in a
|
|
* very small window right after one CPU updated cycle_last under
|
|
* xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
|
|
* is smaller than the cycle_last reference value due to a TSC which
|
|
* is slighty behind. This delta is nowhere else observable, but in
|
|
* that case it results in a forward time jump in the range of hours
|
|
* due to the unsigned delta calculation of the time keeping core
|
|
* code, which is necessary to support wrapping clocksources like pm
|
|
* timer.
|
|
*/
|
|
static cycle_t read_tsc(struct clocksource *cs)
|
|
{
|
|
cycle_t ret = (cycle_t)get_cycles();
|
|
|
|
return ret >= clocksource_tsc.cycle_last ?
|
|
ret : clocksource_tsc.cycle_last;
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
static cycle_t __vsyscall_fn vread_tsc(void)
|
|
{
|
|
cycle_t ret;
|
|
|
|
/*
|
|
* Surround the RDTSC by barriers, to make sure it's not
|
|
* speculated to outside the seqlock critical section and
|
|
* does not cause time warps:
|
|
*/
|
|
rdtsc_barrier();
|
|
ret = (cycle_t)vget_cycles();
|
|
rdtsc_barrier();
|
|
|
|
return ret >= __vsyscall_gtod_data.clock.cycle_last ?
|
|
ret : __vsyscall_gtod_data.clock.cycle_last;
|
|
}
|
|
#endif
|
|
|
|
static void resume_tsc(struct clocksource *cs)
|
|
{
|
|
clocksource_tsc.cycle_last = 0;
|
|
}
|
|
|
|
static struct clocksource clocksource_tsc = {
|
|
.name = "tsc",
|
|
.rating = 300,
|
|
.read = read_tsc,
|
|
.resume = resume_tsc,
|
|
.mask = CLOCKSOURCE_MASK(64),
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
|
|
CLOCK_SOURCE_MUST_VERIFY,
|
|
#ifdef CONFIG_X86_64
|
|
.vread = vread_tsc,
|
|
#endif
|
|
};
|
|
|
|
void mark_tsc_unstable(char *reason)
|
|
{
|
|
if (!tsc_unstable) {
|
|
tsc_unstable = 1;
|
|
sched_clock_stable = 0;
|
|
printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
|
|
/* Change only the rating, when not registered */
|
|
if (clocksource_tsc.mult)
|
|
clocksource_mark_unstable(&clocksource_tsc);
|
|
else {
|
|
clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
|
|
clocksource_tsc.rating = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(mark_tsc_unstable);
|
|
|
|
static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
|
|
{
|
|
printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
|
|
d->ident);
|
|
tsc_unstable = 1;
|
|
return 0;
|
|
}
|
|
|
|
/* List of systems that have known TSC problems */
|
|
static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
|
|
{
|
|
.callback = dmi_mark_tsc_unstable,
|
|
.ident = "IBM Thinkpad 380XD",
|
|
.matches = {
|
|
DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
|
|
DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
|
|
},
|
|
},
|
|
{}
|
|
};
|
|
|
|
static void __init check_system_tsc_reliable(void)
|
|
{
|
|
#ifdef CONFIG_MGEODE_LX
|
|
/* RTSC counts during suspend */
|
|
#define RTSC_SUSP 0x100
|
|
unsigned long res_low, res_high;
|
|
|
|
rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
|
|
/* Geode_LX - the OLPC CPU has a very reliable TSC */
|
|
if (res_low & RTSC_SUSP)
|
|
tsc_clocksource_reliable = 1;
|
|
#endif
|
|
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
|
|
tsc_clocksource_reliable = 1;
|
|
}
|
|
|
|
/*
|
|
* Make an educated guess if the TSC is trustworthy and synchronized
|
|
* over all CPUs.
|
|
*/
|
|
__cpuinit int unsynchronized_tsc(void)
|
|
{
|
|
if (!cpu_has_tsc || tsc_unstable)
|
|
return 1;
|
|
|
|
#ifdef CONFIG_SMP
|
|
if (apic_is_clustered_box())
|
|
return 1;
|
|
#endif
|
|
|
|
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
|
|
return 0;
|
|
/*
|
|
* Intel systems are normally all synchronized.
|
|
* Exceptions must mark TSC as unstable:
|
|
*/
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
|
|
/* assume multi socket systems are not synchronized: */
|
|
if (num_possible_cpus() > 1)
|
|
tsc_unstable = 1;
|
|
}
|
|
|
|
return tsc_unstable;
|
|
}
|
|
|
|
static void __init init_tsc_clocksource(void)
|
|
{
|
|
if (tsc_clocksource_reliable)
|
|
clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
|
|
/* lower the rating if we already know its unstable: */
|
|
if (check_tsc_unstable()) {
|
|
clocksource_tsc.rating = 0;
|
|
clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
|
|
}
|
|
clocksource_register_khz(&clocksource_tsc, tsc_khz);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
/*
|
|
* calibrate_cpu is used on systems with fixed rate TSCs to determine
|
|
* processor frequency
|
|
*/
|
|
#define TICK_COUNT 100000000
|
|
static unsigned long __init calibrate_cpu(void)
|
|
{
|
|
int tsc_start, tsc_now;
|
|
int i, no_ctr_free;
|
|
unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
|
|
unsigned long flags;
|
|
|
|
for (i = 0; i < 4; i++)
|
|
if (avail_to_resrv_perfctr_nmi_bit(i))
|
|
break;
|
|
no_ctr_free = (i == 4);
|
|
if (no_ctr_free) {
|
|
WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
|
|
"cpu_khz value may be incorrect.\n");
|
|
i = 3;
|
|
rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
|
|
wrmsrl(MSR_K7_EVNTSEL3, 0);
|
|
rdmsrl(MSR_K7_PERFCTR3, pmc3);
|
|
} else {
|
|
reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
|
|
reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
|
|
}
|
|
local_irq_save(flags);
|
|
/* start measuring cycles, incrementing from 0 */
|
|
wrmsrl(MSR_K7_PERFCTR0 + i, 0);
|
|
wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
|
|
rdtscl(tsc_start);
|
|
do {
|
|
rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
|
|
tsc_now = get_cycles();
|
|
} while ((tsc_now - tsc_start) < TICK_COUNT);
|
|
|
|
local_irq_restore(flags);
|
|
if (no_ctr_free) {
|
|
wrmsrl(MSR_K7_EVNTSEL3, 0);
|
|
wrmsrl(MSR_K7_PERFCTR3, pmc3);
|
|
wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
|
|
} else {
|
|
release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
|
|
release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
|
|
}
|
|
|
|
return pmc_now * tsc_khz / (tsc_now - tsc_start);
|
|
}
|
|
#else
|
|
static inline unsigned long calibrate_cpu(void) { return cpu_khz; }
|
|
#endif
|
|
|
|
void __init tsc_init(void)
|
|
{
|
|
u64 lpj;
|
|
int cpu;
|
|
|
|
x86_init.timers.tsc_pre_init();
|
|
|
|
if (!cpu_has_tsc)
|
|
return;
|
|
|
|
tsc_khz = x86_platform.calibrate_tsc();
|
|
cpu_khz = tsc_khz;
|
|
|
|
if (!tsc_khz) {
|
|
mark_tsc_unstable("could not calculate TSC khz");
|
|
return;
|
|
}
|
|
|
|
if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
|
|
(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
|
|
cpu_khz = calibrate_cpu();
|
|
|
|
printk("Detected %lu.%03lu MHz processor.\n",
|
|
(unsigned long)cpu_khz / 1000,
|
|
(unsigned long)cpu_khz % 1000);
|
|
|
|
/*
|
|
* Secondary CPUs do not run through tsc_init(), so set up
|
|
* all the scale factors for all CPUs, assuming the same
|
|
* speed as the bootup CPU. (cpufreq notifiers will fix this
|
|
* up if their speed diverges)
|
|
*/
|
|
for_each_possible_cpu(cpu)
|
|
set_cyc2ns_scale(cpu_khz, cpu);
|
|
|
|
if (tsc_disabled > 0)
|
|
return;
|
|
|
|
/* now allow native_sched_clock() to use rdtsc */
|
|
tsc_disabled = 0;
|
|
|
|
lpj = ((u64)tsc_khz * 1000);
|
|
do_div(lpj, HZ);
|
|
lpj_fine = lpj;
|
|
|
|
use_tsc_delay();
|
|
/* Check and install the TSC clocksource */
|
|
dmi_check_system(bad_tsc_dmi_table);
|
|
|
|
if (unsynchronized_tsc())
|
|
mark_tsc_unstable("TSCs unsynchronized");
|
|
|
|
check_system_tsc_reliable();
|
|
init_tsc_clocksource();
|
|
}
|
|
|