Stephen Boyd d10ebc7c64 Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next ... - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes		2023-08-30 14:37:45 -07:00
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Kconfig	clk: starfive: Add StarFive JH7110 Video-Output clock driver	2023-07-19 18:08:05 +01:00
Makefile	clk: starfive: Add StarFive JH7110 Video-Output clock driver	2023-07-19 18:08:05 +01:00
clk-starfive-jh71x0.c	clk: starfive: Simplify .determine_rate()	2023-07-19 12:50:42 -07:00
clk-starfive-jh71x0.h	clk: starfive: Rename "jh7100" to "jh71x0" for the common code	2023-04-05 15:43:42 +01:00
clk-starfive-jh7100-audio.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
clk-starfive-jh7100.c	clk: starfive: Rename "jh7100" to "jh71x0" for the common code	2023-04-05 15:43:42 +01:00
clk-starfive-jh7110-aon.c	clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers	2023-04-17 18:14:10 -07:00
clk-starfive-jh7110-isp.c	clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver	2023-07-19 18:08:05 +01:00
clk-starfive-jh7110-pll.c	clk: starfive: Add StarFive JH7110 PLL clock driver	2023-07-19 18:08:00 +01:00
clk-starfive-jh7110-stg.c	clk: starfive: Add StarFive JH7110 System-Top-Group clock driver	2023-07-19 18:08:05 +01:00
clk-starfive-jh7110-sys.c	clk: starfive: jh7110-sys: Add PLL clocks source from DTS	2023-07-19 18:08:00 +01:00
clk-starfive-jh7110-vout.c	clk: starfive: Add StarFive JH7110 Video-Output clock driver	2023-07-19 18:08:05 +01:00
clk-starfive-jh7110.h	clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver	2023-07-19 18:08:05 +01:00