623 lines
15 KiB
C
623 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
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#define SLEEPM BIT(0)
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#define OPMODE_MASK GENMASK(4, 3)
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#define OPMODE_NORMAL (0x00)
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#define OPMODE_NONDRIVING BIT(3)
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#define TERMSEL BIT(5)
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#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
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#define XCVRSEL BIT(0)
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#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
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#define POR BIT(1)
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
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#define SIDDQ BIT(2)
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#define RETENABLEN BIT(3)
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#define FSEL_MASK GENMASK(6, 4)
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#define FSEL_DEFAULT (0x3 << 4)
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
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#define VBUSVLDEXTSEL0 BIT(4)
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#define PLLBTUNE BIT(5)
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
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#define VREGBYPASS BIT(0)
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
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#define VBUSVLDEXT0 BIT(0)
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#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
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#define USB2_AUTO_RESUME BIT(0)
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#define USB2_SUSPEND_N BIT(2)
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#define USB2_SUSPEND_N_SEL BIT(3)
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#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c)
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#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70)
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#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74)
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#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78)
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#define PARAM_OVRD_MASK 0xFF
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#define USB2_PHY_USB_PHY_CFG0 (0x94)
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#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
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#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
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#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
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#define REFCLK_SEL_MASK GENMASK(1, 0)
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#define REFCLK_SEL_DEFAULT (0x2 << 0)
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#define HS_DISCONNECT_MASK GENMASK(2, 0)
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#define SQUELCH_DETECTOR_MASK GENMASK(7, 5)
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#define HS_AMPLITUDE_MASK GENMASK(3, 0)
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#define PREEMPHASIS_DURATION_MASK BIT(5)
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#define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6)
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#define HS_RISE_FALL_MASK GENMASK(1, 0)
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#define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2)
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#define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4)
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#define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0)
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static const char * const qcom_snps_hsphy_vreg_names[] = {
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"vdda-pll", "vdda33", "vdda18",
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};
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#define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
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struct override_param {
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s32 value;
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u8 reg_val;
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};
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struct override_param_map {
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const char *prop_name;
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const struct override_param *param_table;
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u8 table_size;
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u8 reg_offset;
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u8 param_mask;
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};
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struct phy_override_seq {
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bool need_update;
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u8 offset;
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u8 value;
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u8 mask;
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};
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#define NUM_HSPHY_TUNING_PARAMS (9)
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/**
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* struct qcom_snps_hsphy - snps hs phy attributes
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*
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* @phy: generic phy
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* @base: iomapped memory space for snps hs phy
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*
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* @cfg_ahb_clk: AHB2PHY interface clock
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* @ref_clk: phy reference clock
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* @iface_clk: phy interface clock
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* @phy_reset: phy reset control
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* @vregs: regulator supplies bulk data
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* @phy_initialized: if PHY has been initialized correctly
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* @mode: contains the current mode the PHY is in
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*/
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struct qcom_snps_hsphy {
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struct phy *phy;
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void __iomem *base;
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struct clk *cfg_ahb_clk;
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struct clk *ref_clk;
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struct reset_control *phy_reset;
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struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
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bool phy_initialized;
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enum phy_mode mode;
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struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS];
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};
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static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
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u32 mask, u32 val)
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{
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u32 reg;
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reg = readl_relaxed(base + offset);
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reg &= ~mask;
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reg |= val & mask;
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writel_relaxed(reg, base + offset);
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/* Ensure above write is completed */
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readl_relaxed(base + offset);
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}
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static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
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{
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dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
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if (hsphy->mode == PHY_MODE_USB_HOST) {
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/* Enable auto-resume to meet remote wakeup timing */
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qcom_snps_hsphy_write_mask(hsphy->base,
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USB2_PHY_USB_PHY_HS_PHY_CTRL2,
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USB2_AUTO_RESUME,
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USB2_AUTO_RESUME);
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usleep_range(500, 1000);
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qcom_snps_hsphy_write_mask(hsphy->base,
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USB2_PHY_USB_PHY_HS_PHY_CTRL2,
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0, USB2_AUTO_RESUME);
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}
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clk_disable_unprepare(hsphy->cfg_ahb_clk);
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return 0;
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}
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static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
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{
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int ret;
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dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
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ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
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if (ret) {
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dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");
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return ret;
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}
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return 0;
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}
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static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
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{
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struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
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if (!hsphy->phy_initialized)
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return 0;
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qcom_snps_hsphy_suspend(hsphy);
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return 0;
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}
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static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
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{
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struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
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if (!hsphy->phy_initialized)
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return 0;
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qcom_snps_hsphy_resume(hsphy);
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return 0;
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}
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static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
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int submode)
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{
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struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
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hsphy->mode = mode;
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return 0;
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}
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static const struct override_param hs_disconnect_sc7280[] = {
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{ -272, 0 },
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{ 0, 1 },
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{ 317, 2 },
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{ 630, 3 },
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{ 973, 4 },
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{ 1332, 5 },
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{ 1743, 6 },
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{ 2156, 7 },
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};
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static const struct override_param squelch_det_threshold_sc7280[] = {
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{ -2090, 7 },
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{ -1560, 6 },
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{ -1030, 5 },
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{ -530, 4 },
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{ 0, 3 },
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{ 530, 2 },
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{ 1060, 1 },
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{ 1590, 0 },
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};
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static const struct override_param hs_amplitude_sc7280[] = {
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{ -660, 0 },
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{ -440, 1 },
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{ -220, 2 },
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{ 0, 3 },
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{ 230, 4 },
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{ 440, 5 },
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{ 650, 6 },
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{ 890, 7 },
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{ 1110, 8 },
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{ 1330, 9 },
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{ 1560, 10 },
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{ 1780, 11 },
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{ 2000, 12 },
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{ 2220, 13 },
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{ 2430, 14 },
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{ 2670, 15 },
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};
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static const struct override_param preemphasis_duration_sc7280[] = {
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{ 10000, 1 },
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{ 20000, 0 },
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};
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static const struct override_param preemphasis_amplitude_sc7280[] = {
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{ 10000, 1 },
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{ 20000, 2 },
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{ 30000, 3 },
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{ 40000, 0 },
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};
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static const struct override_param hs_rise_fall_time_sc7280[] = {
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{ -4100, 3 },
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{ 0, 2 },
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{ 2810, 1 },
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{ 5430, 0 },
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};
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static const struct override_param hs_crossover_voltage_sc7280[] = {
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{ -31000, 1 },
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{ 0, 3 },
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{ 28000, 2 },
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};
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static const struct override_param hs_output_impedance_sc7280[] = {
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{ -2300000, 3 },
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{ 0, 2 },
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{ 2600000, 1 },
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{ 6100000, 0 },
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};
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static const struct override_param ls_fs_output_impedance_sc7280[] = {
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{ -1053, 15 },
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{ -557, 7 },
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{ 0, 3 },
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{ 612, 1 },
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{ 1310, 0 },
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};
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static const struct override_param_map sc7280_snps_7nm_phy[] = {
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{
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"qcom,hs-disconnect-bp",
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hs_disconnect_sc7280,
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ARRAY_SIZE(hs_disconnect_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
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HS_DISCONNECT_MASK
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},
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{
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"qcom,squelch-detector-bp",
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squelch_det_threshold_sc7280,
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ARRAY_SIZE(squelch_det_threshold_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0,
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SQUELCH_DETECTOR_MASK
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},
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{
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"qcom,hs-amplitude-bp",
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hs_amplitude_sc7280,
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ARRAY_SIZE(hs_amplitude_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
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HS_AMPLITUDE_MASK
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},
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{
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"qcom,pre-emphasis-duration-bp",
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preemphasis_duration_sc7280,
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ARRAY_SIZE(preemphasis_duration_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
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PREEMPHASIS_DURATION_MASK,
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},
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{
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"qcom,pre-emphasis-amplitude-bp",
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preemphasis_amplitude_sc7280,
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ARRAY_SIZE(preemphasis_amplitude_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1,
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PREEMPHASIS_AMPLITUDE_MASK,
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},
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{
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"qcom,hs-rise-fall-time-bp",
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hs_rise_fall_time_sc7280,
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ARRAY_SIZE(hs_rise_fall_time_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
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HS_RISE_FALL_MASK
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},
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{
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"qcom,hs-crossover-voltage-microvolt",
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hs_crossover_voltage_sc7280,
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ARRAY_SIZE(hs_crossover_voltage_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
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HS_CROSSOVER_VOLTAGE_MASK
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},
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{
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"qcom,hs-output-impedance-micro-ohms",
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hs_output_impedance_sc7280,
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ARRAY_SIZE(hs_output_impedance_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2,
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HS_OUTPUT_IMPEDANCE_MASK,
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},
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{
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"qcom,ls-fs-output-impedance-bp",
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ls_fs_output_impedance_sc7280,
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ARRAY_SIZE(ls_fs_output_impedance_sc7280),
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USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3,
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LS_FS_OUTPUT_IMPEDANCE_MASK,
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},
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{},
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};
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static int qcom_snps_hsphy_init(struct phy *phy)
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{
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struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
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int ret, i;
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dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
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ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
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if (ret)
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return ret;
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ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
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if (ret) {
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dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
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goto poweroff_phy;
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}
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ret = reset_control_assert(hsphy->phy_reset);
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if (ret) {
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dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
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goto disable_ahb_clk;
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}
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usleep_range(100, 150);
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ret = reset_control_deassert(hsphy->phy_reset);
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if (ret) {
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dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
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goto disable_ahb_clk;
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}
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
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UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
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UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
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POR, POR);
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qcom_snps_hsphy_write_mask(hsphy->base,
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
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FSEL_MASK, 0);
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qcom_snps_hsphy_write_mask(hsphy->base,
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
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PLLBTUNE, PLLBTUNE);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
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REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
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qcom_snps_hsphy_write_mask(hsphy->base,
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
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VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
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VBUSVLDEXT0, VBUSVLDEXT0);
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for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {
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if (hsphy->update_seq_cfg[i].need_update)
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qcom_snps_hsphy_write_mask(hsphy->base,
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hsphy->update_seq_cfg[i].offset,
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hsphy->update_seq_cfg[i].mask,
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hsphy->update_seq_cfg[i].value);
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}
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qcom_snps_hsphy_write_mask(hsphy->base,
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USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
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VREGBYPASS, VREGBYPASS);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
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USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
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SLEEPM, SLEEPM);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
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SIDDQ, 0);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
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POR, 0);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
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USB2_SUSPEND_N_SEL, 0);
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qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
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UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
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hsphy->phy_initialized = true;
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return 0;
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disable_ahb_clk:
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clk_disable_unprepare(hsphy->cfg_ahb_clk);
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poweroff_phy:
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regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
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return ret;
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}
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static int qcom_snps_hsphy_exit(struct phy *phy)
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{
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struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
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reset_control_assert(hsphy->phy_reset);
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clk_disable_unprepare(hsphy->cfg_ahb_clk);
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regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
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hsphy->phy_initialized = false;
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return 0;
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}
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static const struct phy_ops qcom_snps_hsphy_gen_ops = {
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.init = qcom_snps_hsphy_init,
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.exit = qcom_snps_hsphy_exit,
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.set_mode = qcom_snps_hsphy_set_mode,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
|
|
{ .compatible = "qcom,sm8150-usb-hs-phy", },
|
|
{ .compatible = "qcom,usb-snps-hs-5nm-phy", },
|
|
{
|
|
.compatible = "qcom,usb-snps-hs-7nm-phy",
|
|
.data = &sc7280_snps_7nm_phy,
|
|
},
|
|
{ .compatible = "qcom,usb-snps-femto-v2-phy", },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
|
|
|
|
static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
|
|
qcom_snps_hsphy_runtime_resume, NULL)
|
|
};
|
|
|
|
static void qcom_snps_hsphy_override_param_update_val(
|
|
const struct override_param_map map,
|
|
s32 dt_val, struct phy_override_seq *seq_entry)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Param table for each param is in increasing order
|
|
* of dt values. We need to iterate over the list to
|
|
* select the entry that matches the dt value and pick
|
|
* up the corresponding register value.
|
|
*/
|
|
for (i = 0; i < map.table_size - 1; i++) {
|
|
if (map.param_table[i].value == dt_val)
|
|
break;
|
|
}
|
|
|
|
seq_entry->need_update = true;
|
|
seq_entry->offset = map.reg_offset;
|
|
seq_entry->mask = map.param_mask;
|
|
seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask);
|
|
}
|
|
|
|
static void qcom_snps_hsphy_read_override_param_seq(struct device *dev)
|
|
{
|
|
struct device_node *node = dev->of_node;
|
|
s32 val;
|
|
int ret, i;
|
|
struct qcom_snps_hsphy *hsphy;
|
|
const struct override_param_map *cfg = of_device_get_match_data(dev);
|
|
|
|
if (!cfg)
|
|
return;
|
|
|
|
hsphy = dev_get_drvdata(dev);
|
|
|
|
for (i = 0; cfg[i].prop_name != NULL; i++) {
|
|
ret = of_property_read_s32(node, cfg[i].prop_name, &val);
|
|
if (ret)
|
|
continue;
|
|
|
|
qcom_snps_hsphy_override_param_update_val(cfg[i], val,
|
|
&hsphy->update_seq_cfg[i]);
|
|
dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n",
|
|
cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value);
|
|
|
|
}
|
|
}
|
|
|
|
static int qcom_snps_hsphy_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct qcom_snps_hsphy *hsphy;
|
|
struct phy_provider *phy_provider;
|
|
struct phy *generic_phy;
|
|
int ret, i;
|
|
int num;
|
|
|
|
hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
|
|
if (!hsphy)
|
|
return -ENOMEM;
|
|
|
|
hsphy->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(hsphy->base))
|
|
return PTR_ERR(hsphy->base);
|
|
|
|
hsphy->ref_clk = devm_clk_get(dev, "ref");
|
|
if (IS_ERR(hsphy->ref_clk))
|
|
return dev_err_probe(dev, PTR_ERR(hsphy->ref_clk),
|
|
"failed to get ref clk\n");
|
|
|
|
hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
|
|
if (IS_ERR(hsphy->phy_reset)) {
|
|
dev_err(dev, "failed to get phy core reset\n");
|
|
return PTR_ERR(hsphy->phy_reset);
|
|
}
|
|
|
|
num = ARRAY_SIZE(hsphy->vregs);
|
|
for (i = 0; i < num; i++)
|
|
hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
|
|
|
|
ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret,
|
|
"failed to get regulator supplies\n");
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
/*
|
|
* Prevent runtime pm from being ON by default. Users can enable
|
|
* it using power/control in sysfs.
|
|
*/
|
|
pm_runtime_forbid(dev);
|
|
|
|
generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
|
|
if (IS_ERR(generic_phy)) {
|
|
ret = PTR_ERR(generic_phy);
|
|
dev_err(dev, "failed to create phy, %d\n", ret);
|
|
return ret;
|
|
}
|
|
hsphy->phy = generic_phy;
|
|
|
|
dev_set_drvdata(dev, hsphy);
|
|
phy_set_drvdata(generic_phy, hsphy);
|
|
qcom_snps_hsphy_read_override_param_seq(dev);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
if (!IS_ERR(phy_provider))
|
|
dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
|
|
else
|
|
pm_runtime_disable(dev);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static struct platform_driver qcom_snps_hsphy_driver = {
|
|
.probe = qcom_snps_hsphy_probe,
|
|
.driver = {
|
|
.name = "qcom-snps-hs-femto-v2-phy",
|
|
.pm = &qcom_snps_hsphy_pm_ops,
|
|
.of_match_table = qcom_snps_hsphy_of_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(qcom_snps_hsphy_driver);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
|
|
MODULE_LICENSE("GPL v2");
|