725 lines
18 KiB
C
725 lines
18 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "amdgpu.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_vce.h"
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#include "cikd.h"
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/* 1 second timeout */
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#define VCE_IDLE_TIMEOUT_MS 1000
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/* Firmware Names */
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#ifdef CONFIG_DRM_AMDGPU_CIK
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#define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
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#define FIRMWARE_KABINI "radeon/kabini_vce.bin"
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#define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
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#define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
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#define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
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#endif
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#define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
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#define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
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#ifdef CONFIG_DRM_AMDGPU_CIK
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MODULE_FIRMWARE(FIRMWARE_BONAIRE);
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MODULE_FIRMWARE(FIRMWARE_KABINI);
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MODULE_FIRMWARE(FIRMWARE_KAVERI);
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MODULE_FIRMWARE(FIRMWARE_HAWAII);
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MODULE_FIRMWARE(FIRMWARE_MULLINS);
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#endif
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MODULE_FIRMWARE(FIRMWARE_TONGA);
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MODULE_FIRMWARE(FIRMWARE_CARRIZO);
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static void amdgpu_vce_idle_work_handler(struct work_struct *work);
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/**
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* amdgpu_vce_init - allocate memory, load vce firmware
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*
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* @adev: amdgpu_device pointer
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*
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* First step to get VCE online, allocate memory and load the firmware
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*/
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int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
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{
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const char *fw_name;
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const struct common_firmware_header *hdr;
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unsigned ucode_version, version_major, version_minor, binary_id;
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int i, r;
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INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
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switch (adev->asic_type) {
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_BONAIRE:
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fw_name = FIRMWARE_BONAIRE;
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break;
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case CHIP_KAVERI:
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fw_name = FIRMWARE_KAVERI;
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break;
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case CHIP_KABINI:
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fw_name = FIRMWARE_KABINI;
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break;
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case CHIP_HAWAII:
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fw_name = FIRMWARE_HAWAII;
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break;
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case CHIP_MULLINS:
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fw_name = FIRMWARE_MULLINS;
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break;
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#endif
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case CHIP_TONGA:
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fw_name = FIRMWARE_TONGA;
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break;
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case CHIP_CARRIZO:
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fw_name = FIRMWARE_CARRIZO;
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break;
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default:
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return -EINVAL;
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}
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r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
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if (r) {
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dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n",
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fw_name);
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return r;
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}
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r = amdgpu_ucode_validate(adev->vce.fw);
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if (r) {
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dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->vce.fw);
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adev->vce.fw = NULL;
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return r;
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}
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hdr = (const struct common_firmware_header *)adev->vce.fw->data;
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ucode_version = le32_to_cpu(hdr->ucode_version);
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version_major = (ucode_version >> 20) & 0xfff;
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version_minor = (ucode_version >> 8) & 0xfff;
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binary_id = ucode_version & 0xff;
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DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
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version_major, version_minor, binary_id);
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adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |
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(binary_id << 8));
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/* allocate firmware, stack and heap BO */
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r = amdgpu_bo_create(adev, size, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
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return r;
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}
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r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
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if (r) {
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amdgpu_bo_unref(&adev->vce.vcpu_bo);
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dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
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return r;
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}
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r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
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&adev->vce.gpu_addr);
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amdgpu_bo_unreserve(adev->vce.vcpu_bo);
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if (r) {
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amdgpu_bo_unref(&adev->vce.vcpu_bo);
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dev_err(adev->dev, "(%d) VCE bo pin failed\n", r);
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return r;
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}
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for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
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atomic_set(&adev->vce.handles[i], 0);
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adev->vce.filp[i] = NULL;
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}
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return 0;
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}
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/**
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* amdgpu_vce_fini - free memory
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*
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* @adev: amdgpu_device pointer
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*
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* Last step on VCE teardown, free firmware memory
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*/
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int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
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{
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if (adev->vce.vcpu_bo == NULL)
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return 0;
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amdgpu_bo_unref(&adev->vce.vcpu_bo);
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amdgpu_ring_fini(&adev->vce.ring[0]);
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amdgpu_ring_fini(&adev->vce.ring[1]);
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release_firmware(adev->vce.fw);
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return 0;
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}
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/**
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* amdgpu_vce_suspend - unpin VCE fw memory
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*
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* @adev: amdgpu_device pointer
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*
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*/
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int amdgpu_vce_suspend(struct amdgpu_device *adev)
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{
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int i;
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if (adev->vce.vcpu_bo == NULL)
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return 0;
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for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
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if (atomic_read(&adev->vce.handles[i]))
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break;
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if (i == AMDGPU_MAX_VCE_HANDLES)
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return 0;
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/* TODO: suspending running encoding sessions isn't supported */
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return -EINVAL;
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}
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/**
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* amdgpu_vce_resume - pin VCE fw memory
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*
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* @adev: amdgpu_device pointer
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*
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*/
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int amdgpu_vce_resume(struct amdgpu_device *adev)
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{
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void *cpu_addr;
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const struct common_firmware_header *hdr;
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unsigned offset;
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int r;
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if (adev->vce.vcpu_bo == NULL)
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return -EINVAL;
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r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);
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if (r) {
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dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r);
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return r;
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}
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r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);
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if (r) {
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amdgpu_bo_unreserve(adev->vce.vcpu_bo);
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dev_err(adev->dev, "(%d) VCE map failed\n", r);
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return r;
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}
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hdr = (const struct common_firmware_header *)adev->vce.fw->data;
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offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
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memcpy(cpu_addr, (adev->vce.fw->data) + offset,
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(adev->vce.fw->size) - offset);
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amdgpu_bo_kunmap(adev->vce.vcpu_bo);
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amdgpu_bo_unreserve(adev->vce.vcpu_bo);
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return 0;
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}
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/**
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* amdgpu_vce_idle_work_handler - power off VCE
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*
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* @work: pointer to work structure
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*
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* power of VCE when it's not used any more
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*/
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static void amdgpu_vce_idle_work_handler(struct work_struct *work)
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{
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, vce.idle_work.work);
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if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) &&
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(amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) {
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if (adev->pm.dpm_enabled) {
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amdgpu_dpm_enable_vce(adev, false);
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} else {
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amdgpu_asic_set_vce_clocks(adev, 0, 0);
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}
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} else {
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schedule_delayed_work(&adev->vce.idle_work,
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msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
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}
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}
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/**
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* amdgpu_vce_note_usage - power up VCE
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*
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* @adev: amdgpu_device pointer
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*
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* Make sure VCE is powerd up when we want to use it
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*/
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static void amdgpu_vce_note_usage(struct amdgpu_device *adev)
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{
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bool streams_changed = false;
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bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
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set_clocks &= schedule_delayed_work(&adev->vce.idle_work,
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msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
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if (adev->pm.dpm_enabled) {
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/* XXX figure out if the streams changed */
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streams_changed = false;
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}
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if (set_clocks || streams_changed) {
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if (adev->pm.dpm_enabled) {
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amdgpu_dpm_enable_vce(adev, true);
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} else {
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amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
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}
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}
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}
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/**
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* amdgpu_vce_free_handles - free still open VCE handles
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*
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* @adev: amdgpu_device pointer
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* @filp: drm file pointer
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*
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* Close all VCE handles still open by this file pointer
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*/
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void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
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{
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struct amdgpu_ring *ring = &adev->vce.ring[0];
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int i, r;
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for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
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uint32_t handle = atomic_read(&adev->vce.handles[i]);
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if (!handle || adev->vce.filp[i] != filp)
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continue;
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amdgpu_vce_note_usage(adev);
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r = amdgpu_vce_get_destroy_msg(ring, handle, NULL);
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if (r)
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DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
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adev->vce.filp[i] = NULL;
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atomic_set(&adev->vce.handles[i], 0);
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}
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}
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/**
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* amdgpu_vce_get_create_msg - generate a VCE create msg
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*
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* @adev: amdgpu_device pointer
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* @ring: ring we should submit the msg to
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* @handle: VCE session handle to use
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* @fence: optional fence to return
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*
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* Open up a stream for HW test
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*/
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int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
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struct amdgpu_fence **fence)
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{
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const unsigned ib_size_dw = 1024;
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struct amdgpu_ib ib;
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uint64_t dummy;
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int i, r;
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r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib);
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if (r) {
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DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
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return r;
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}
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dummy = ib.gpu_addr + 1024;
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/* stitch together an VCE create msg */
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ib.length_dw = 0;
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ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
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ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
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ib.ptr[ib.length_dw++] = handle;
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ib.ptr[ib.length_dw++] = 0x00000030; /* len */
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ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
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ib.ptr[ib.length_dw++] = 0x00000000;
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ib.ptr[ib.length_dw++] = 0x00000042;
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ib.ptr[ib.length_dw++] = 0x0000000a;
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ib.ptr[ib.length_dw++] = 0x00000001;
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ib.ptr[ib.length_dw++] = 0x00000080;
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ib.ptr[ib.length_dw++] = 0x00000060;
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ib.ptr[ib.length_dw++] = 0x00000100;
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ib.ptr[ib.length_dw++] = 0x00000100;
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ib.ptr[ib.length_dw++] = 0x0000000c;
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ib.ptr[ib.length_dw++] = 0x00000000;
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ib.ptr[ib.length_dw++] = 0x00000014; /* len */
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ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
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ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
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ib.ptr[ib.length_dw++] = dummy;
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ib.ptr[ib.length_dw++] = 0x00000001;
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for (i = ib.length_dw; i < ib_size_dw; ++i)
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ib.ptr[i] = 0x0;
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r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
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if (r) {
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DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
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}
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if (fence)
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*fence = amdgpu_fence_ref(ib.fence);
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amdgpu_ib_free(ring->adev, &ib);
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return r;
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}
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/**
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* amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
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*
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* @adev: amdgpu_device pointer
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* @ring: ring we should submit the msg to
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* @handle: VCE session handle to use
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* @fence: optional fence to return
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*
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* Close up a stream for HW test or if userspace failed to do so
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*/
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int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
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struct amdgpu_fence **fence)
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{
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const unsigned ib_size_dw = 1024;
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struct amdgpu_ib ib;
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uint64_t dummy;
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int i, r;
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r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib);
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if (r) {
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DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
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return r;
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}
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dummy = ib.gpu_addr + 1024;
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/* stitch together an VCE destroy msg */
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ib.length_dw = 0;
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ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
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ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
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ib.ptr[ib.length_dw++] = handle;
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ib.ptr[ib.length_dw++] = 0x00000014; /* len */
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ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
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ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
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ib.ptr[ib.length_dw++] = dummy;
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ib.ptr[ib.length_dw++] = 0x00000001;
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ib.ptr[ib.length_dw++] = 0x00000008; /* len */
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ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
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for (i = ib.length_dw; i < ib_size_dw; ++i)
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ib.ptr[i] = 0x0;
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r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
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if (r) {
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DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
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}
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if (fence)
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*fence = amdgpu_fence_ref(ib.fence);
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amdgpu_ib_free(ring->adev, &ib);
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return r;
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}
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/**
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* amdgpu_vce_cs_reloc - command submission relocation
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*
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* @p: parser context
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* @lo: address of lower dword
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* @hi: address of higher dword
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*
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* Patch relocation inside command stream with real buffer address
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*/
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int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi)
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{
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struct amdgpu_bo_va_mapping *mapping;
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struct amdgpu_ib *ib = &p->ibs[ib_idx];
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struct amdgpu_bo *bo;
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uint64_t addr;
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addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
|
|
((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
|
|
|
|
mapping = amdgpu_cs_find_mapping(p, addr, &bo);
|
|
if (mapping == NULL) {
|
|
DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d\n",
|
|
addr, lo, hi);
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
|
|
addr += amdgpu_bo_gpu_offset(bo);
|
|
|
|
ib->ptr[lo] = addr & 0xFFFFFFFF;
|
|
ib->ptr[hi] = addr >> 32;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_vce_cs_parse - parse and validate the command stream
|
|
*
|
|
* @p: parser context
|
|
*
|
|
*/
|
|
int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
|
|
{
|
|
uint32_t handle = 0;
|
|
bool destroy = false;
|
|
int i, r, idx = 0;
|
|
struct amdgpu_ib *ib = &p->ibs[ib_idx];
|
|
|
|
amdgpu_vce_note_usage(p->adev);
|
|
|
|
while (idx < ib->length_dw) {
|
|
uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
|
|
uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
|
|
|
|
if ((len < 8) || (len & 3)) {
|
|
DRM_ERROR("invalid VCE command length (%d)!\n", len);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (cmd) {
|
|
case 0x00000001: // session
|
|
handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
|
|
break;
|
|
|
|
case 0x00000002: // task info
|
|
case 0x01000001: // create
|
|
case 0x04000001: // config extension
|
|
case 0x04000002: // pic control
|
|
case 0x04000005: // rate control
|
|
case 0x04000007: // motion estimation
|
|
case 0x04000008: // rdo
|
|
case 0x04000009: // vui
|
|
case 0x05000002: // auxiliary buffer
|
|
break;
|
|
|
|
case 0x03000001: // encode
|
|
r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11);
|
|
if (r)
|
|
return r;
|
|
break;
|
|
|
|
case 0x02000001: // destroy
|
|
destroy = true;
|
|
break;
|
|
|
|
case 0x05000001: // context buffer
|
|
case 0x05000004: // video bitstream buffer
|
|
case 0x05000005: // feedback buffer
|
|
r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2);
|
|
if (r)
|
|
return r;
|
|
break;
|
|
|
|
default:
|
|
DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
|
|
return -EINVAL;
|
|
}
|
|
|
|
idx += len / 4;
|
|
}
|
|
|
|
if (destroy) {
|
|
/* IB contains a destroy msg, free the handle */
|
|
for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i)
|
|
atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* create or encode, validate the handle */
|
|
for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
|
|
if (atomic_read(&p->adev->vce.handles[i]) == handle)
|
|
return 0;
|
|
}
|
|
|
|
/* handle not found try to alloc a new one */
|
|
for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
|
|
if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {
|
|
p->adev->vce.filp[i] = p->filp;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
DRM_ERROR("No more free VCE handles!\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_vce_ring_emit_semaphore - emit a semaphore command
|
|
*
|
|
* @ring: engine to use
|
|
* @semaphore: address of semaphore
|
|
* @emit_wait: true=emit wait, false=emit signal
|
|
*
|
|
*/
|
|
bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring,
|
|
struct amdgpu_semaphore *semaphore,
|
|
bool emit_wait)
|
|
{
|
|
uint64_t addr = semaphore->gpu_addr;
|
|
|
|
amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE);
|
|
amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);
|
|
amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);
|
|
amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
|
|
if (!emit_wait)
|
|
amdgpu_ring_write(ring, VCE_CMD_END);
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_vce_ring_emit_ib - execute indirect buffer
|
|
*
|
|
* @ring: engine to use
|
|
* @ib: the IB to execute
|
|
*
|
|
*/
|
|
void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
|
|
{
|
|
amdgpu_ring_write(ring, VCE_CMD_IB);
|
|
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
|
|
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
|
|
amdgpu_ring_write(ring, ib->length_dw);
|
|
}
|
|
|
|
/**
|
|
* amdgpu_vce_ring_emit_fence - add a fence command to the ring
|
|
*
|
|
* @ring: engine to use
|
|
* @fence: the fence
|
|
*
|
|
*/
|
|
void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
|
|
bool write64bits)
|
|
{
|
|
WARN_ON(write64bits);
|
|
|
|
amdgpu_ring_write(ring, VCE_CMD_FENCE);
|
|
amdgpu_ring_write(ring, addr);
|
|
amdgpu_ring_write(ring, upper_32_bits(addr));
|
|
amdgpu_ring_write(ring, seq);
|
|
amdgpu_ring_write(ring, VCE_CMD_TRAP);
|
|
amdgpu_ring_write(ring, VCE_CMD_END);
|
|
}
|
|
|
|
/**
|
|
* amdgpu_vce_ring_test_ring - test if VCE ring is working
|
|
*
|
|
* @ring: the engine to test on
|
|
*
|
|
*/
|
|
int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
uint32_t rptr = amdgpu_ring_get_rptr(ring);
|
|
unsigned i;
|
|
int r;
|
|
|
|
r = amdgpu_ring_lock(ring, 16);
|
|
if (r) {
|
|
DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
|
|
ring->idx, r);
|
|
return r;
|
|
}
|
|
amdgpu_ring_write(ring, VCE_CMD_END);
|
|
amdgpu_ring_unlock_commit(ring);
|
|
|
|
for (i = 0; i < adev->usec_timeout; i++) {
|
|
if (amdgpu_ring_get_rptr(ring) != rptr)
|
|
break;
|
|
DRM_UDELAY(1);
|
|
}
|
|
|
|
if (i < adev->usec_timeout) {
|
|
DRM_INFO("ring test on %d succeeded in %d usecs\n",
|
|
ring->idx, i);
|
|
} else {
|
|
DRM_ERROR("amdgpu: ring %d test failed\n",
|
|
ring->idx);
|
|
r = -ETIMEDOUT;
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_vce_ring_test_ib - test if VCE IBs are working
|
|
*
|
|
* @ring: the engine to test on
|
|
*
|
|
*/
|
|
int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_fence *fence = NULL;
|
|
int r;
|
|
|
|
r = amdgpu_vce_get_create_msg(ring, 1, NULL);
|
|
if (r) {
|
|
DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
|
|
goto error;
|
|
}
|
|
|
|
r = amdgpu_vce_get_destroy_msg(ring, 1, &fence);
|
|
if (r) {
|
|
DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
|
|
goto error;
|
|
}
|
|
|
|
r = amdgpu_fence_wait(fence, false);
|
|
if (r) {
|
|
DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
|
|
} else {
|
|
DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
|
|
}
|
|
error:
|
|
amdgpu_fence_unref(&fence);
|
|
return r;
|
|
}
|