67 lines
1.2 KiB
Plaintext
67 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on "omap4.dtsi"
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*/
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#include "dra7.dtsi"
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/ {
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compatible = "ti,dra722", "ti,dra72", "ti,dra7";
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupt-parent = <&wakeupgen>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&dss {
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reg = <0x58000000 0x80>,
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<0x58004054 0x4>,
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<0x58004300 0x20>;
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reg-names = "dss", "pll1_clkctrl", "pll1";
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clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
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<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
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clock-names = "fck", "video1_clk";
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};
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&mailbox5 {
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mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
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ti,mbox-tx = <6 2 2>;
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ti,mbox-rx = <4 2 2>;
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status = "disabled";
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};
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mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
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ti,mbox-tx = <5 2 2>;
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ti,mbox-rx = <1 2 2>;
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status = "disabled";
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};
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};
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&mailbox6 {
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mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
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ti,mbox-tx = <6 2 2>;
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ti,mbox-rx = <4 2 2>;
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status = "disabled";
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};
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};
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&pcie1_rc {
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compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
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};
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&pcie1_ep {
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compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
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};
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&pcie2_rc {
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compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
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};
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&usb4_tm {
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status = "disabled";
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};
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