493 lines
12 KiB
C
493 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* iio/adc/max1027.c
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* Copyright (C) 2014 Philippe Reynes
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*
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* based on linux/drivers/iio/ad7923.c
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* Copyright 2011 Analog Devices Inc (from AD7923 Driver)
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* Copyright 2012 CS Systemes d'Information
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*
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* max1027.c
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*
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* Partial support for max1027 and similar chips.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spi/spi.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#define MAX1027_CONV_REG BIT(7)
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#define MAX1027_SETUP_REG BIT(6)
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#define MAX1027_AVG_REG BIT(5)
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#define MAX1027_RST_REG BIT(4)
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/* conversion register */
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#define MAX1027_TEMP BIT(0)
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#define MAX1027_SCAN_0_N (0x00 << 1)
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#define MAX1027_SCAN_N_M (0x01 << 1)
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#define MAX1027_SCAN_N (0x02 << 1)
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#define MAX1027_NOSCAN (0x03 << 1)
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#define MAX1027_CHAN(n) ((n) << 3)
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/* setup register */
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#define MAX1027_UNIPOLAR 0x02
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#define MAX1027_BIPOLAR 0x03
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#define MAX1027_REF_MODE0 (0x00 << 2)
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#define MAX1027_REF_MODE1 (0x01 << 2)
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#define MAX1027_REF_MODE2 (0x02 << 2)
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#define MAX1027_REF_MODE3 (0x03 << 2)
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#define MAX1027_CKS_MODE0 (0x00 << 4)
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#define MAX1027_CKS_MODE1 (0x01 << 4)
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#define MAX1027_CKS_MODE2 (0x02 << 4)
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#define MAX1027_CKS_MODE3 (0x03 << 4)
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/* averaging register */
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#define MAX1027_NSCAN_4 0x00
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#define MAX1027_NSCAN_8 0x01
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#define MAX1027_NSCAN_12 0x02
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#define MAX1027_NSCAN_16 0x03
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#define MAX1027_NAVG_4 (0x00 << 2)
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#define MAX1027_NAVG_8 (0x01 << 2)
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#define MAX1027_NAVG_16 (0x02 << 2)
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#define MAX1027_NAVG_32 (0x03 << 2)
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#define MAX1027_AVG_EN BIT(4)
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enum max1027_id {
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max1027,
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max1029,
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max1031,
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};
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static const struct spi_device_id max1027_id[] = {
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{"max1027", max1027},
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{"max1029", max1029},
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{"max1031", max1031},
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{}
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};
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MODULE_DEVICE_TABLE(spi, max1027_id);
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#ifdef CONFIG_OF
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static const struct of_device_id max1027_adc_dt_ids[] = {
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{ .compatible = "maxim,max1027" },
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{ .compatible = "maxim,max1029" },
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{ .compatible = "maxim,max1031" },
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{},
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};
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MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
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#endif
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#define MAX1027_V_CHAN(index) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = index, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = index + 1, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 10, \
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.storagebits = 16, \
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.shift = 2, \
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.endianness = IIO_BE, \
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}, \
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}
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#define MAX1027_T_CHAN \
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{ \
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.type = IIO_TEMP, \
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.channel = 0, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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.scan_index = 0, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 12, \
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.storagebits = 16, \
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.endianness = IIO_BE, \
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}, \
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}
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static const struct iio_chan_spec max1027_channels[] = {
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MAX1027_T_CHAN,
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MAX1027_V_CHAN(0),
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MAX1027_V_CHAN(1),
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MAX1027_V_CHAN(2),
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MAX1027_V_CHAN(3),
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MAX1027_V_CHAN(4),
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MAX1027_V_CHAN(5),
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MAX1027_V_CHAN(6),
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MAX1027_V_CHAN(7)
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};
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static const struct iio_chan_spec max1029_channels[] = {
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MAX1027_T_CHAN,
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MAX1027_V_CHAN(0),
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MAX1027_V_CHAN(1),
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MAX1027_V_CHAN(2),
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MAX1027_V_CHAN(3),
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MAX1027_V_CHAN(4),
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MAX1027_V_CHAN(5),
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MAX1027_V_CHAN(6),
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MAX1027_V_CHAN(7),
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MAX1027_V_CHAN(8),
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MAX1027_V_CHAN(9),
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MAX1027_V_CHAN(10),
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MAX1027_V_CHAN(11)
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};
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static const struct iio_chan_spec max1031_channels[] = {
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MAX1027_T_CHAN,
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MAX1027_V_CHAN(0),
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MAX1027_V_CHAN(1),
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MAX1027_V_CHAN(2),
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MAX1027_V_CHAN(3),
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MAX1027_V_CHAN(4),
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MAX1027_V_CHAN(5),
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MAX1027_V_CHAN(6),
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MAX1027_V_CHAN(7),
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MAX1027_V_CHAN(8),
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MAX1027_V_CHAN(9),
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MAX1027_V_CHAN(10),
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MAX1027_V_CHAN(11),
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MAX1027_V_CHAN(12),
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MAX1027_V_CHAN(13),
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MAX1027_V_CHAN(14),
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MAX1027_V_CHAN(15)
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};
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static const unsigned long max1027_available_scan_masks[] = {
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0x000001ff,
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0x00000000,
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};
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static const unsigned long max1029_available_scan_masks[] = {
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0x00001fff,
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0x00000000,
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};
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static const unsigned long max1031_available_scan_masks[] = {
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0x0001ffff,
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0x00000000,
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};
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struct max1027_chip_info {
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const struct iio_chan_spec *channels;
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unsigned int num_channels;
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const unsigned long *available_scan_masks;
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};
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static const struct max1027_chip_info max1027_chip_info_tbl[] = {
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[max1027] = {
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.channels = max1027_channels,
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.num_channels = ARRAY_SIZE(max1027_channels),
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.available_scan_masks = max1027_available_scan_masks,
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},
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[max1029] = {
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.channels = max1029_channels,
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.num_channels = ARRAY_SIZE(max1029_channels),
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.available_scan_masks = max1029_available_scan_masks,
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},
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[max1031] = {
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.channels = max1031_channels,
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.num_channels = ARRAY_SIZE(max1031_channels),
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.available_scan_masks = max1031_available_scan_masks,
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},
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};
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struct max1027_state {
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const struct max1027_chip_info *info;
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struct spi_device *spi;
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struct iio_trigger *trig;
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__be16 *buffer;
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struct mutex lock;
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u8 reg ____cacheline_aligned;
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};
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static int max1027_read_single_value(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val)
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{
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int ret;
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struct max1027_state *st = iio_priv(indio_dev);
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if (iio_buffer_enabled(indio_dev)) {
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dev_warn(&indio_dev->dev, "trigger mode already enabled");
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return -EBUSY;
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}
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/* Start acquisition on conversion register write */
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st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0) {
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dev_err(&indio_dev->dev,
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"Failed to configure setup register\n");
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return ret;
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}
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/* Configure conversion register with the requested chan */
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st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
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MAX1027_NOSCAN;
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if (chan->type == IIO_TEMP)
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st->reg |= MAX1027_TEMP;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0) {
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dev_err(&indio_dev->dev,
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"Failed to configure conversion register\n");
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return ret;
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}
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/*
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* For an unknown reason, when we use the mode "10" (write
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* conversion register), the interrupt doesn't occur every time.
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* So we just wait 1 ms.
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*/
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mdelay(1);
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/* Read result */
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ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
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if (ret < 0)
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return ret;
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*val = be16_to_cpu(st->buffer[0]);
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return IIO_VAL_INT;
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}
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static int max1027_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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int ret = 0;
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struct max1027_state *st = iio_priv(indio_dev);
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mutex_lock(&st->lock);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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ret = max1027_read_single_value(indio_dev, chan, val);
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break;
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case IIO_CHAN_INFO_SCALE:
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switch (chan->type) {
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case IIO_TEMP:
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*val = 1;
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*val2 = 8;
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ret = IIO_VAL_FRACTIONAL;
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break;
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case IIO_VOLTAGE:
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*val = 2500;
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*val2 = 10;
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ret = IIO_VAL_FRACTIONAL_LOG2;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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mutex_unlock(&st->lock);
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return ret;
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}
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static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
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unsigned reg, unsigned writeval,
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unsigned *readval)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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u8 *val = (u8 *)st->buffer;
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if (readval != NULL)
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return -EINVAL;
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*val = (u8)writeval;
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return spi_write(st->spi, val, 1);
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}
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static int max1027_validate_trigger(struct iio_dev *indio_dev,
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struct iio_trigger *trig)
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{
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struct max1027_state *st = iio_priv(indio_dev);
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if (st->trig != trig)
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return -EINVAL;
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return 0;
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}
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static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
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{
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struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
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struct max1027_state *st = iio_priv(indio_dev);
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int ret;
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if (state) {
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/* Start acquisition on cnvst */
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st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
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MAX1027_REF_MODE2;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0)
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return ret;
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/* Scan from 0 to max */
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st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
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MAX1027_SCAN_N_M | MAX1027_TEMP;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0)
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return ret;
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} else {
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/* Start acquisition on conversion register write */
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st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
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MAX1027_REF_MODE2;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static irqreturn_t max1027_trigger_handler(int irq, void *private)
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{
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struct iio_poll_func *pf = private;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct max1027_state *st = iio_priv(indio_dev);
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pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
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/* fill buffer with all channel */
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spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
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iio_push_to_buffers(indio_dev, st->buffer);
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static const struct iio_trigger_ops max1027_trigger_ops = {
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.validate_device = &iio_trigger_validate_own_device,
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.set_trigger_state = &max1027_set_trigger_state,
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};
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static const struct iio_info max1027_info = {
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.read_raw = &max1027_read_raw,
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.validate_trigger = &max1027_validate_trigger,
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.debugfs_reg_access = &max1027_debugfs_reg_access,
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};
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static int max1027_probe(struct spi_device *spi)
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{
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int ret;
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struct iio_dev *indio_dev;
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struct max1027_state *st;
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pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (indio_dev == NULL) {
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pr_err("Can't allocate iio device\n");
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return -ENOMEM;
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}
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spi_set_drvdata(spi, indio_dev);
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st = iio_priv(indio_dev);
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st->spi = spi;
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st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
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mutex_init(&st->lock);
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indio_dev->name = spi_get_device_id(spi)->name;
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indio_dev->dev.parent = &spi->dev;
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indio_dev->dev.of_node = spi->dev.of_node;
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indio_dev->info = &max1027_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = st->info->channels;
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indio_dev->num_channels = st->info->num_channels;
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indio_dev->available_scan_masks = st->info->available_scan_masks;
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st->buffer = devm_kmalloc_array(&indio_dev->dev,
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indio_dev->num_channels, 2,
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GFP_KERNEL);
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if (st->buffer == NULL) {
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dev_err(&indio_dev->dev, "Can't allocate buffer\n");
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return -ENOMEM;
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}
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ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
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&iio_pollfunc_store_time,
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&max1027_trigger_handler, NULL);
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if (ret < 0) {
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dev_err(&indio_dev->dev, "Failed to setup buffer\n");
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return ret;
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}
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st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
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indio_dev->name);
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if (st->trig == NULL) {
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ret = -ENOMEM;
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dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
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return ret;
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}
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st->trig->ops = &max1027_trigger_ops;
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st->trig->dev.parent = &spi->dev;
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iio_trigger_set_drvdata(st->trig, indio_dev);
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iio_trigger_register(st->trig);
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ret = devm_request_threaded_irq(&spi->dev, spi->irq,
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iio_trigger_generic_data_rdy_poll,
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NULL,
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IRQF_TRIGGER_FALLING,
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spi->dev.driver->name, st->trig);
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if (ret < 0) {
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dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
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return ret;
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}
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/* Internal reset */
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st->reg = MAX1027_RST_REG;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0) {
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dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
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return ret;
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}
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/* Disable averaging */
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st->reg = MAX1027_AVG_REG;
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ret = spi_write(st->spi, &st->reg, 1);
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if (ret < 0) {
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dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
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return ret;
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}
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return devm_iio_device_register(&spi->dev, indio_dev);
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}
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static struct spi_driver max1027_driver = {
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.driver = {
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.name = "max1027",
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.of_match_table = of_match_ptr(max1027_adc_dt_ids),
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},
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.probe = max1027_probe,
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.id_table = max1027_id,
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};
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module_spi_driver(max1027_driver);
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MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
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MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
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MODULE_LICENSE("GPL v2");
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