397 lines
17 KiB
ReStructuredText
397 lines
17 KiB
ReStructuredText
=================================================
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FPGA Device Feature List (DFL) Framework Overview
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=================================================
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Authors:
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- Enno Luebbers <enno.luebbers@intel.com>
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- Xiao Guangrong <guangrong.xiao@linux.intel.com>
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- Wu Hao <hao.wu@intel.com>
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The Device Feature List (DFL) FPGA framework (and drivers according to this
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this framework) hides the very details of low layer hardwares and provides
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unified interfaces to userspace. Applications could use these interfaces to
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configure, enumerate, open and access FPGA accelerators on platforms which
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implement the DFL in the device memory. Besides this, the DFL framework
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enables system level management functions such as FPGA reconfiguration.
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Device Feature List (DFL) Overview
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==================================
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Device Feature List (DFL) defines a linked list of feature headers within the
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device MMIO space to provide an extensible way of adding features. Software can
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walk through these predefined data structures to enumerate FPGA features:
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FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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as illustrated below::
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Header Header Header Header
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+----------+ +-->+----------+ +-->+----------+ +-->+----------+
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| Type | | | Type | | | Type | | | Type |
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| FIU | | | Private | | | Private | | | Private |
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+----------+ | | Feature | | | Feature | | | Feature |
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| Next_DFH |--+ +----------+ | +----------+ | +----------+
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+----------+ | Next_DFH |--+ | Next_DFH |--+ | Next_DFH |--> NULL
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| ID | +----------+ +----------+ +----------+
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+----------+ | ID | | ID | | ID |
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| Next_AFU |--+ +----------+ +----------+ +----------+
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+----------+ | | Feature | | Feature | | Feature |
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| Header | | | Register | | Register | | Register |
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| Register | | | Set | | Set | | Set |
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| Set | | +----------+ +----------+ +----------+
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+----------+ | Header
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+-->+----------+
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| Type |
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| AFU |
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+----------+
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| Next_DFH |--> NULL
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+----------+
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| GUID |
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+----------+
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| Header |
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| Register |
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| Set |
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+----------+
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FPGA Interface Unit (FIU) represents a standalone functional unit for the
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interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
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descriptions on FME and Port in later sections).
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Accelerated Function Unit (AFU) represents a FPGA programmable region and
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always connects to a FIU (e.g. a Port) as its child as illustrated above.
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Private Features represent sub features of the FIU and AFU. They could be
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various function blocks with different IDs, but all private features which
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belong to the same FIU or AFU, must be linked to one list via the Next Device
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Feature Header (Next_DFH) pointer.
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Each FIU, AFU and Private Feature could implement its own functional registers.
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The functional register set for FIU and AFU, is named as Header Register Set,
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e.g. FME Header Register Set, and the one for Private Feature, is named as
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Feature Register Set, e.g. FME Partial Reconfiguration Feature Register Set.
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This Device Feature List provides a way of linking features together, it's
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convenient for software to locate each feature by walking through this list,
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and can be implemented in register regions of any FPGA device.
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FIU - FME (FPGA Management Engine)
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==================================
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The FPGA Management Engine performs reconfiguration and other infrastructure
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functions. Each FPGA device only has one FME.
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User-space applications can acquire exclusive access to the FME using open(),
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and release it using close().
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The following functions are exposed through ioctls:
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- Get driver API version (DFL_FPGA_GET_API_VERSION)
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- Check for extensions (DFL_FPGA_CHECK_EXTENSION)
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- Program bitstream (DFL_FPGA_FME_PORT_PR)
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- Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
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- Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
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More functions are exposed through sysfs
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(/sys/class/fpga_region/regionX/dfl-fme.n/):
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Read bitstream ID (bitstream_id)
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bitstream_id indicates version of the static FPGA region.
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Read bitstream metadata (bitstream_metadata)
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bitstream_metadata includes detailed information of static FPGA region,
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e.g. synthesis date and seed.
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Read number of ports (ports_num)
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one FPGA device may have more than one port, this sysfs interface indicates
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how many ports the FPGA device has.
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Global error reporting management (errors/)
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error reporting sysfs interfaces allow user to read errors detected by the
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hardware, and clear the logged errors.
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FIU - PORT
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==========
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A port represents the interface between the static FPGA fabric and a partially
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reconfigurable region containing an AFU. It controls the communication from SW
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to the accelerator and exposes features such as reset and debug. Each FPGA
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device may have more than one port, but always one AFU per port.
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AFU
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===
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An AFU is attached to a port FIU and exposes a fixed length MMIO region to be
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used for accelerator-specific control registers.
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User-space applications can acquire exclusive access to an AFU attached to a
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port by using open() on the port device node and release it using close().
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The following functions are exposed through ioctls:
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- Get driver API version (DFL_FPGA_GET_API_VERSION)
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- Check for extensions (DFL_FPGA_CHECK_EXTENSION)
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- Get port info (DFL_FPGA_PORT_GET_INFO)
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- Get MMIO region info (DFL_FPGA_PORT_GET_REGION_INFO)
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- Map DMA buffer (DFL_FPGA_PORT_DMA_MAP)
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- Unmap DMA buffer (DFL_FPGA_PORT_DMA_UNMAP)
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- Reset AFU (DFL_FPGA_PORT_RESET)
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DFL_FPGA_PORT_RESET:
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reset the FPGA Port and its AFU. Userspace can do Port
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reset at any time, e.g. during DMA or Partial Reconfiguration. But it should
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never cause any system level issue, only functional failure (e.g. DMA or PR
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operation failure) and be recoverable from the failure.
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User-space applications can also mmap() accelerator MMIO regions.
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More functions are exposed through sysfs:
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(/sys/class/fpga_region/<regionX>/<dfl-port.m>/):
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Read Accelerator GUID (afu_id)
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afu_id indicates which PR bitstream is programmed to this AFU.
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Error reporting (errors/)
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error reporting sysfs interfaces allow user to read port/afu errors
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detected by the hardware, and clear the logged errors.
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DFL Framework Overview
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======================
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::
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+----------+ +--------+ +--------+ +--------+
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| FME | | AFU | | AFU | | AFU |
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| Module | | Module | | Module | | Module |
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+----------+ +--------+ +--------+ +--------+
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+-----------------------+
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| FPGA Container Device | Device Feature List
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| (FPGA Base Region) | Framework
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+-----------------------+
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------------------------------------------------------------------
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+----------------------------+
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| FPGA DFL Device Module |
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| (e.g. PCIE/Platform Device)|
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+----------------------------+
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+------------------------+
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| FPGA Hardware Device |
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+------------------------+
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DFL framework in kernel provides common interfaces to create container device
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(FPGA base region), discover feature devices and their private features from the
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given Device Feature Lists and create platform devices for feature devices
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(e.g. FME, Port and AFU) with related resources under the container device. It
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also abstracts operations for the private features and exposes common ops to
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feature device drivers.
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The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform
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device and etc. Its driver module is always loaded first once the device is
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created by the system. This driver plays an infrastructural role in the
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driver architecture. It locates the DFLs in the device memory, handles them
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and related resources to common interfaces from DFL framework for enumeration.
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(Please refer to drivers/fpga/dfl.c for detailed enumeration APIs).
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The FPGA Management Engine (FME) driver is a platform driver which is loaded
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automatically after FME platform device creation from the DFL device module. It
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provides the key features for FPGA management, including:
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a) Expose static FPGA region information, e.g. version and metadata.
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Users can read related information via sysfs interfaces exposed
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by FME driver.
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b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
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bridges and FPGA regions during PR sub feature initialization. Once
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it receives a DFL_FPGA_FME_PORT_PR ioctl from user, it invokes the
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common interface function from FPGA Region to complete the partial
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reconfiguration of the PR bitstream to the given port.
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Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
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probed once the AFU platform device is created. The main function of this module
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is to provide an interface for userspace applications to access the individual
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accelerators, including basic reset control on port, AFU MMIO region export, dma
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buffer mapping service functions.
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After feature platform devices creation, matched platform drivers will be loaded
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automatically to handle different functionalities. Please refer to next sections
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for detailed information on functional units which have been already implemented
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under this DFL framework.
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Partial Reconfiguration
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=======================
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As mentioned above, accelerators can be reconfigured through partial
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reconfiguration of a PR bitstream file. The PR bitstream file must have been
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generated for the exact static FPGA region and targeted reconfigurable region
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(port) of the FPGA, otherwise, the reconfiguration operation will fail and
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possibly cause system instability. This compatibility can be checked by
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comparing the compatibility ID noted in the header of PR bitstream file against
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the compat_id exposed by the target FPGA region. This check is usually done by
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userspace before calling the reconfiguration IOCTL.
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FPGA virtualization - PCIe SRIOV
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================================
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This section describes the virtualization support on DFL based FPGA device to
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enable accessing an accelerator from applications running in a virtual machine
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(VM). This section only describes the PCIe based FPGA device with SRIOV support.
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Features supported by the particular FPGA device are exposed through Device
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Feature Lists, as illustrated below:
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::
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+-------------------------------+ +-------------+
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| PF | | VF |
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+-------------------------------+ +-------------+
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^ ^ ^ ^
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| | | |
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+-----|------------|---------|--------------|-------+
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| | | | | |
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| +-----+ +-------+ +-------+ +-------+ |
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| | FME | | Port0 | | Port1 | | Port2 | |
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| +-----+ +-------+ +-------+ +-------+ |
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| ^ ^ ^ |
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| | | | |
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| +-------+ +------+ +-------+ |
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| | AFU | | AFU | | AFU | |
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| +-------+ +------+ +-------+ |
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| DFL based FPGA PCIe Device |
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+---------------------------------------------------+
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FME is always accessed through the physical function (PF).
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Ports (and related AFUs) are accessed via PF by default, but could be exposed
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through virtual function (VF) devices via PCIe SRIOV. Each VF only contains
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1 Port and 1 AFU for isolation. Users could assign individual VFs (accelerators)
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created via PCIe SRIOV interface, to virtual machines.
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The driver organization in virtualization case is illustrated below:
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::
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+-------++------++------+ |
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| FME || FME || FME | |
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| FPGA || FPGA || FPGA | |
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|Manager||Bridge||Region| |
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+-------++------++------+ |
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+-----------------------+ +--------+ | +--------+
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| FME | | AFU | | | AFU |
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| Module | | Module | | | Module |
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+-----------------------+ +--------+ | +--------+
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+-----------------------+ | +-----------------------+
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| FPGA Container Device | | | FPGA Container Device |
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| (FPGA Base Region) | | | (FPGA Base Region) |
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+-----------------------+ | +-----------------------+
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+------------------+ | +------------------+
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| FPGA PCIE Module | | Virtual | FPGA PCIE Module |
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+------------------+ Host | Machine +------------------+
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-------------------------------------- | ------------------------------
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+---------------+ | +---------------+
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| PCI PF Device | | | PCI VF Device |
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+---------------+ | +---------------+
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FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device
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is detected. It:
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* Finishes enumeration on both FPGA PCIe PF and VF device using common
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interfaces from DFL framework.
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* Supports SRIOV.
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The FME device driver plays a management role in this driver architecture, it
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provides ioctls to release Port from PF and assign Port to PF. After release
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a port from PF, then it's safe to expose this port through a VF via PCIe SRIOV
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sysfs interface.
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To enable accessing an accelerator from applications running in a VM, the
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respective AFU's port needs to be assigned to a VF using the following steps:
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#. The PF owns all AFU ports by default. Any port that needs to be
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reassigned to a VF must first be released through the
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DFL_FPGA_FME_PORT_RELEASE ioctl on the FME device.
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#. Once N ports are released from PF, then user can use command below
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to enable SRIOV and VFs. Each VF owns only one Port with AFU.
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::
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echo N > $PCI_DEVICE_PATH/sriov_numvfs
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#. Pass through the VFs to VMs
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#. The AFU under VF is accessible from applications in VM (using the
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same driver inside the VF).
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Note that an FME can't be assigned to a VF, thus PR and other management
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functions are only available via the PF.
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Device enumeration
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==================
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This section introduces how applications enumerate the fpga device from
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the sysfs hierarchy under /sys/class/fpga_region.
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In the example below, two DFL based FPGA devices are installed in the host. Each
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fpga device has one FME and two ports (AFUs).
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FPGA regions are created under /sys/class/fpga_region/::
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/sys/class/fpga_region/region0
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/sys/class/fpga_region/region1
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/sys/class/fpga_region/region2
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...
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Application needs to search each regionX folder, if feature device is found,
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(e.g. "dfl-port.n" or "dfl-fme.m" is found), then it's the base
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fpga region which represents the FPGA device.
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Each base region has one FME and two ports (AFUs) as child devices::
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/sys/class/fpga_region/region0/dfl-fme.0
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/sys/class/fpga_region/region0/dfl-port.0
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/sys/class/fpga_region/region0/dfl-port.1
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...
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/sys/class/fpga_region/region3/dfl-fme.1
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/sys/class/fpga_region/region3/dfl-port.2
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/sys/class/fpga_region/region3/dfl-port.3
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...
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In general, the FME/AFU sysfs interfaces are named as follows::
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/sys/class/fpga_region/<regionX>/<dfl-fme.n>/
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/sys/class/fpga_region/<regionX>/<dfl-port.m>/
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with 'n' consecutively numbering all FMEs and 'm' consecutively numbering all
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ports.
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The device nodes used for ioctl() or mmap() can be referenced through::
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/sys/class/fpga_region/<regionX>/<dfl-fme.n>/dev
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/sys/class/fpga_region/<regionX>/<dfl-port.n>/dev
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Add new FIUs support
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====================
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It's possible that developers made some new function blocks (FIUs) under this
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DFL framework, then new platform device driver needs to be developed for the
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new feature dev (FIU) following the same way as existing feature dev drivers
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(e.g. FME and Port/AFU platform device driver). Besides that, it requires
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modification on DFL framework enumeration code too, for new FIU type detection
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and related platform devices creation.
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Add new private features support
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================================
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In some cases, we may need to add some new private features to existing FIUs
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(e.g. FME or Port). Developers don't need to touch enumeration code in DFL
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framework, as each private feature will be parsed automatically and related
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mmio resources can be found under FIU platform device created by DFL framework.
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Developer only needs to provide a sub feature driver with matched feature id.
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FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
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could be a reference.
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Open discussion
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===============
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FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
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to user now. In the future, if unified user interfaces for reconfiguration are
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added, FME driver should switch to them from ioctl interface.
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