766 lines
19 KiB
C
766 lines
19 KiB
C
/* $Id: gpio.c,v 1.16 2005/06/19 17:06:49 starvik Exp $
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*
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* ETRAX CRISv32 general port I/O device
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*
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* Copyright (c) 1999, 2000, 2001, 2002, 2003 Axis Communications AB
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*
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* Authors: Bjorn Wesen (initial version)
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* Ola Knutsson (LED handling)
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* Johan Adolfsson (read/set directions, write, port G,
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* port to ETRAX FS.
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*
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* $Log: gpio.c,v $
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* Revision 1.16 2005/06/19 17:06:49 starvik
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* Merge of Linux 2.6.12.
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*
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* Revision 1.15 2005/05/25 08:22:20 starvik
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* Changed GPIO port order to fit packages/devices/axis-2.4.
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*
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* Revision 1.14 2005/04/24 18:35:08 starvik
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* Updated with final register headers.
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*
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* Revision 1.13 2005/03/15 15:43:00 starvik
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* dev_id needs to be supplied for shared IRQs.
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*
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* Revision 1.12 2005/03/10 17:12:00 starvik
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* Protect alarm list with spinlock.
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*
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* Revision 1.11 2005/01/05 06:08:59 starvik
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* No need to do local_irq_disable after local_irq_save.
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*
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* Revision 1.10 2004/11/19 08:38:31 starvik
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* Removed old crap.
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*
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* Revision 1.9 2004/05/14 07:58:02 starvik
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* Merge of changes from 2.4
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*
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* Revision 1.8 2003/09/11 07:29:50 starvik
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* Merge of Linux 2.6.0-test5
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*
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* Revision 1.7 2003/07/10 13:25:46 starvik
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* Compiles for 2.5.74
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* Lindented ethernet.c
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*
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* Revision 1.6 2003/07/04 08:27:46 starvik
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* Merge of Linux 2.5.74
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*
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* Revision 1.5 2003/06/10 08:26:37 johana
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* Etrax -> ETRAX CRISv32
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*
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* Revision 1.4 2003/06/05 14:22:48 johana
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* Initialise some_alarms.
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*
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* Revision 1.3 2003/06/05 10:15:46 johana
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* New INTR_VECT macros.
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* Enable interrupts in global config.
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*
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* Revision 1.2 2003/06/03 15:52:50 johana
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* Initial CRIS v32 version.
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*
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* Revision 1.1 2003/06/03 08:53:15 johana
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* Copy of os/lx25/arch/cris/arch-v10/drivers/gpio.c version 1.7.
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*
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/string.h>
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#include <linux/poll.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/etraxgpio.h>
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#include <asm/arch/hwregs/reg_map.h>
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/gio_defs.h>
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#include <asm/arch/hwregs/intr_vect_defs.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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/* The following gio ports on ETRAX FS is available:
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* pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
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* pb 18 bits
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* pc 18 bits
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* pd 18 bits
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* pe 18 bits
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* each port has a rw_px_dout, r_px_din and rw_px_oe register.
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*/
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#define GPIO_MAJOR 120 /* experimental MAJOR number */
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#define D(x)
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#if 0
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static int dp_cnt;
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#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
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#else
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#define DP(x)
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#endif
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static char gpio_name[] = "etrax gpio";
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#if 0
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static wait_queue_head_t *gpio_wq;
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#endif
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static int gpio_ioctl(struct inode *inode, struct file *file,
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unsigned int cmd, unsigned long arg);
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static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
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loff_t *off);
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static int gpio_open(struct inode *inode, struct file *filp);
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static int gpio_release(struct inode *inode, struct file *filp);
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static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
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/* private data per open() of this driver */
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struct gpio_private {
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struct gpio_private *next;
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/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
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unsigned char clk_mask;
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unsigned char data_mask;
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unsigned char write_msb;
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unsigned char pad1;
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/* These fields are generic */
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unsigned long highalarm, lowalarm;
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wait_queue_head_t alarm_wq;
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int minor;
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};
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/* linked list of alarms to check for */
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static struct gpio_private *alarmlist = 0;
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static int gpio_some_alarms = 0; /* Set if someone uses alarm */
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static unsigned long gpio_pa_high_alarms = 0;
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static unsigned long gpio_pa_low_alarms = 0;
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static DEFINE_SPINLOCK(alarm_lock);
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#define NUM_PORTS (GPIO_MINOR_LAST+1)
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#define GIO_REG_RD_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg )
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#define GIO_REG_WR_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg )
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unsigned long led_dummy;
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static volatile unsigned long *data_out[NUM_PORTS] = {
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GIO_REG_WR_ADDR(rw_pa_dout),
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GIO_REG_WR_ADDR(rw_pb_dout),
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&led_dummy,
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GIO_REG_WR_ADDR(rw_pc_dout),
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GIO_REG_WR_ADDR(rw_pd_dout),
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GIO_REG_WR_ADDR(rw_pe_dout),
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};
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static volatile unsigned long *data_in[NUM_PORTS] = {
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GIO_REG_RD_ADDR(r_pa_din),
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GIO_REG_RD_ADDR(r_pb_din),
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&led_dummy,
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GIO_REG_RD_ADDR(r_pc_din),
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GIO_REG_RD_ADDR(r_pd_din),
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GIO_REG_RD_ADDR(r_pe_din),
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};
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static unsigned long changeable_dir[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_DIR,
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CONFIG_ETRAX_PB_CHANGEABLE_DIR,
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0,
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CONFIG_ETRAX_PC_CHANGEABLE_DIR,
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CONFIG_ETRAX_PD_CHANGEABLE_DIR,
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CONFIG_ETRAX_PE_CHANGEABLE_DIR,
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};
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static unsigned long changeable_bits[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_BITS,
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CONFIG_ETRAX_PB_CHANGEABLE_BITS,
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0,
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CONFIG_ETRAX_PC_CHANGEABLE_BITS,
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CONFIG_ETRAX_PD_CHANGEABLE_BITS,
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CONFIG_ETRAX_PE_CHANGEABLE_BITS,
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};
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static volatile unsigned long *dir_oe[NUM_PORTS] = {
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GIO_REG_WR_ADDR(rw_pa_oe),
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GIO_REG_WR_ADDR(rw_pb_oe),
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&led_dummy,
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GIO_REG_WR_ADDR(rw_pc_oe),
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GIO_REG_WR_ADDR(rw_pd_oe),
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GIO_REG_WR_ADDR(rw_pe_oe),
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};
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static unsigned int
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gpio_poll(struct file *file,
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poll_table *wait)
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{
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unsigned int mask = 0;
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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unsigned long data;
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poll_wait(file, &priv->alarm_wq, wait);
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if (priv->minor == GPIO_MINOR_A) {
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reg_gio_rw_intr_cfg intr_cfg;
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unsigned long tmp;
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unsigned long flags;
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local_irq_save(flags);
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data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din, REG_RD(gio, regi_gio, r_pa_din));
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/* PA has support for interrupt
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* lets activate high for those low and with highalarm set
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*/
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intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
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tmp = ~data & priv->highalarm & 0xFF;
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if (tmp & (1 << 0)) {
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intr_cfg.pa0 = regk_gio_hi;
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}
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if (tmp & (1 << 1)) {
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intr_cfg.pa1 = regk_gio_hi;
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}
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if (tmp & (1 << 2)) {
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intr_cfg.pa2 = regk_gio_hi;
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}
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if (tmp & (1 << 3)) {
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intr_cfg.pa3 = regk_gio_hi;
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}
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if (tmp & (1 << 4)) {
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intr_cfg.pa4 = regk_gio_hi;
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}
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if (tmp & (1 << 5)) {
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intr_cfg.pa5 = regk_gio_hi;
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}
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if (tmp & (1 << 6)) {
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intr_cfg.pa6 = regk_gio_hi;
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}
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if (tmp & (1 << 7)) {
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intr_cfg.pa7 = regk_gio_hi;
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}
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/*
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* lets activate low for those high and with lowalarm set
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*/
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tmp = data & priv->lowalarm & 0xFF;
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if (tmp & (1 << 0)) {
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intr_cfg.pa0 = regk_gio_lo;
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}
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if (tmp & (1 << 1)) {
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intr_cfg.pa1 = regk_gio_lo;
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}
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if (tmp & (1 << 2)) {
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intr_cfg.pa2 = regk_gio_lo;
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}
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if (tmp & (1 << 3)) {
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intr_cfg.pa3 = regk_gio_lo;
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}
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if (tmp & (1 << 4)) {
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intr_cfg.pa4 = regk_gio_lo;
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}
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if (tmp & (1 << 5)) {
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intr_cfg.pa5 = regk_gio_lo;
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}
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if (tmp & (1 << 6)) {
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intr_cfg.pa6 = regk_gio_lo;
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}
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if (tmp & (1 << 7)) {
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intr_cfg.pa7 = regk_gio_lo;
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}
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REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
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local_irq_restore(flags);
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} else if (priv->minor <= GPIO_MINOR_E)
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data = *data_in[priv->minor];
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else
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return 0;
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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mask = POLLIN|POLLRDNORM;
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}
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DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
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return mask;
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}
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int etrax_gpio_wake_up_check(void)
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{
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struct gpio_private *priv = alarmlist;
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unsigned long data = 0;
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int ret = 0;
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while (priv) {
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data = *data_in[priv->minor];
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
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wake_up_interruptible(&priv->alarm_wq);
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ret = 1;
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}
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priv = priv->next;
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}
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return ret;
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}
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static irqreturn_t
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gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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if (gpio_some_alarms) {
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return IRQ_RETVAL(etrax_gpio_wake_up_check());
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}
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return IRQ_NONE;
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}
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static irqreturn_t
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gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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reg_gio_rw_intr_mask intr_mask;
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reg_gio_r_masked_intr masked_intr;
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reg_gio_rw_ack_intr ack_intr;
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unsigned long tmp;
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unsigned long tmp2;
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/* Find what PA interrupts are active */
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masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
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tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
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/* Find those that we have enabled */
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spin_lock(&alarm_lock);
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tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
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spin_unlock(&alarm_lock);
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/* Ack them */
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ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
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REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
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/* Disable those interrupts.. */
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intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
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tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
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tmp2 &= ~tmp;
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intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
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REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
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if (gpio_some_alarms) {
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return IRQ_RETVAL(etrax_gpio_wake_up_check());
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}
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return IRQ_NONE;
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}
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static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
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loff_t *off)
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{
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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unsigned char data, clk_mask, data_mask, write_msb;
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unsigned long flags;
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unsigned long shadow;
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volatile unsigned long *port;
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ssize_t retval = count;
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/* Only bits 0-7 may be used for write operations but allow all
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devices except leds... */
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if (priv->minor == GPIO_MINOR_LEDS) {
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return -EFAULT;
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}
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if (!access_ok(VERIFY_READ, buf, count)) {
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return -EFAULT;
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}
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clk_mask = priv->clk_mask;
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data_mask = priv->data_mask;
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/* It must have been configured using the IO_CFG_WRITE_MODE */
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/* Perhaps a better error code? */
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if (clk_mask == 0 || data_mask == 0) {
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return -EPERM;
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}
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write_msb = priv->write_msb;
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D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));
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port = data_out[priv->minor];
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while (count--) {
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int i;
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data = *buf++;
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if (priv->write_msb) {
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for (i = 7; i >= 0;i--) {
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local_irq_save(flags);
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shadow = *port;
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*port = shadow &= ~clk_mask;
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if (data & 1<<i)
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*port = shadow |= data_mask;
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else
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*port = shadow &= ~data_mask;
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*port = shadow |= clk_mask;
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local_irq_restore(flags);
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}
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} else {
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for (i = 0; i <= 7;i++) {
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local_irq_save(flags);
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shadow = *port;
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*port = shadow &= ~clk_mask;
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if (data & 1<<i)
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*port = shadow |= data_mask;
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else
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*port = shadow &= ~data_mask;
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*port = shadow |= clk_mask;
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local_irq_restore(flags);
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}
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}
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}
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return retval;
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}
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static int
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gpio_open(struct inode *inode, struct file *filp)
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{
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struct gpio_private *priv;
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int p = iminor(inode);
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if (p > GPIO_MINOR_LAST)
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return -EINVAL;
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priv = kmalloc(sizeof(struct gpio_private),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->minor = p;
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/* initialize the io/alarm struct and link it into our alarmlist */
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priv->next = alarmlist;
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alarmlist = priv;
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priv->clk_mask = 0;
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priv->data_mask = 0;
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priv->highalarm = 0;
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priv->lowalarm = 0;
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init_waitqueue_head(&priv->alarm_wq);
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filp->private_data = (void *)priv;
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return 0;
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}
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static int
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gpio_release(struct inode *inode, struct file *filp)
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{
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struct gpio_private *p = alarmlist;
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struct gpio_private *todel = (struct gpio_private *)filp->private_data;
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/* local copies while updating them: */
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unsigned long a_high, a_low;
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unsigned long some_alarms;
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/* unlink from alarmlist and free the private structure */
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if (p == todel) {
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alarmlist = todel->next;
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} else {
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while (p->next != todel)
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p = p->next;
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p->next = todel->next;
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}
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kfree(todel);
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/* Check if there are still any alarms set */
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p = alarmlist;
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some_alarms = 0;
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a_high = 0;
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a_low = 0;
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while (p) {
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if (p->minor == GPIO_MINOR_A) {
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a_high |= p->highalarm;
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a_low |= p->lowalarm;
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}
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if (p->highalarm | p->lowalarm) {
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some_alarms = 1;
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}
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p = p->next;
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}
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spin_lock(&alarm_lock);
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gpio_some_alarms = some_alarms;
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gpio_pa_high_alarms = a_high;
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gpio_pa_low_alarms = a_low;
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spin_unlock(&alarm_lock);
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return 0;
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}
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/* Main device API. ioctl's to read/set/clear bits, as well as to
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* set alarms to wait for using a subsequent select().
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*/
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unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
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{
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/* Set direction 0=unchanged 1=input,
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* return mask with 1=input
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*/
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unsigned long flags;
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unsigned long dir_shadow;
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local_irq_save(flags);
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dir_shadow = *dir_oe[priv->minor];
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dir_shadow &= ~(arg & changeable_dir[priv->minor]);
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*dir_oe[priv->minor] = dir_shadow;
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local_irq_restore(flags);
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if (priv->minor == GPIO_MINOR_A)
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dir_shadow ^= 0xFF; /* Only 8 bits */
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else
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dir_shadow ^= 0x3FFFF; /* Only 18 bits */
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return dir_shadow;
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} /* setget_input */
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unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
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{
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unsigned long flags;
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unsigned long dir_shadow;
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local_irq_save(flags);
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dir_shadow = *dir_oe[priv->minor];
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dir_shadow |= (arg & changeable_dir[priv->minor]);
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*dir_oe[priv->minor] = dir_shadow;
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local_irq_restore(flags);
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return dir_shadow;
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} /* setget_output */
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static int
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gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
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static int
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gpio_ioctl(struct inode *inode, struct file *file,
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unsigned int cmd, unsigned long arg)
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{
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unsigned long flags;
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unsigned long val;
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unsigned long shadow;
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
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return -EINVAL;
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}
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switch (_IOC_NR(cmd)) {
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case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
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// read the port
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return *data_in[priv->minor];
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break;
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case IO_SETBITS:
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local_irq_save(flags);
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if (arg & 0x04)
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printk("GPIO SET 2\n");
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// set changeable bits with a 1 in arg
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shadow = *data_out[priv->minor];
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shadow |= (arg & changeable_bits[priv->minor]);
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*data_out[priv->minor] = shadow;
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local_irq_restore(flags);
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break;
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case IO_CLRBITS:
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local_irq_save(flags);
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if (arg & 0x04)
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printk("GPIO CLR 2\n");
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// clear changeable bits with a 1 in arg
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shadow = *data_out[priv->minor];
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shadow &= ~(arg & changeable_bits[priv->minor]);
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*data_out[priv->minor] = shadow;
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local_irq_restore(flags);
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break;
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case IO_HIGHALARM:
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// set alarm when bits with 1 in arg go high
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priv->highalarm |= arg;
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spin_lock(&alarm_lock);
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gpio_some_alarms = 1;
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if (priv->minor == GPIO_MINOR_A) {
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gpio_pa_high_alarms |= arg;
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}
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spin_unlock(&alarm_lock);
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break;
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case IO_LOWALARM:
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// set alarm when bits with 1 in arg go low
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priv->lowalarm |= arg;
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spin_lock(&alarm_lock);
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gpio_some_alarms = 1;
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if (priv->minor == GPIO_MINOR_A) {
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gpio_pa_low_alarms |= arg;
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}
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spin_unlock(&alarm_lock);
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break;
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case IO_CLRALARM:
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// clear alarm for bits with 1 in arg
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priv->highalarm &= ~arg;
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priv->lowalarm &= ~arg;
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spin_lock(&alarm_lock);
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if (priv->minor == GPIO_MINOR_A) {
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if (gpio_pa_high_alarms & arg ||
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gpio_pa_low_alarms & arg) {
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/* Must update the gpio_pa_*alarms masks */
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}
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}
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spin_unlock(&alarm_lock);
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break;
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case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
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/* Read direction 0=input 1=output */
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return *dir_oe[priv->minor];
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case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
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/* Set direction 0=unchanged 1=input,
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* return mask with 1=input
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*/
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return setget_input(priv, arg);
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break;
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case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
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/* Set direction 0=unchanged 1=output,
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* return mask with 1=output
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*/
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return setget_output(priv, arg);
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case IO_CFG_WRITE_MODE:
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{
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unsigned long dir_shadow;
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dir_shadow = *dir_oe[priv->minor];
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priv->clk_mask = arg & 0xFF;
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priv->data_mask = (arg >> 8) & 0xFF;
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priv->write_msb = (arg >> 16) & 0x01;
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/* Check if we're allowed to change the bits and
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* the direction is correct
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*/
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if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
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(priv->data_mask & changeable_bits[priv->minor]) &&
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(priv->clk_mask & dir_shadow) &&
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(priv->data_mask & dir_shadow)))
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{
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priv->clk_mask = 0;
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priv->data_mask = 0;
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return -EPERM;
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}
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break;
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}
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case IO_READ_INBITS:
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/* *arg is result of reading the input pins */
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val = *data_in[priv->minor];
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if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
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return -EFAULT;
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return 0;
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break;
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case IO_READ_OUTBITS:
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/* *arg is result of reading the output shadow */
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val = *data_out[priv->minor];
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if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
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return -EFAULT;
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break;
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case IO_SETGET_INPUT:
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/* bits set in *arg is set to input,
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* *arg updated with current input pins.
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*/
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if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
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return -EFAULT;
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val = setget_input(priv, val);
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if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
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return -EFAULT;
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break;
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case IO_SETGET_OUTPUT:
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/* bits set in *arg is set to output,
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* *arg updated with current output pins.
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*/
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if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
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return -EFAULT;
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val = setget_output(priv, val);
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if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
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return -EFAULT;
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break;
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default:
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if (priv->minor == GPIO_MINOR_LEDS)
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return gpio_leds_ioctl(cmd, arg);
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else
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return -EINVAL;
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} /* switch */
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return 0;
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}
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static int
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gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
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{
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unsigned char green;
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unsigned char red;
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switch (_IOC_NR(cmd)) {
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case IO_LEDACTIVE_SET:
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green = ((unsigned char) arg) & 1;
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red = (((unsigned char) arg) >> 1) & 1;
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LED_ACTIVE_SET_G(green);
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LED_ACTIVE_SET_R(red);
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break;
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default:
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return -EINVAL;
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} /* switch */
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return 0;
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}
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const struct file_operations gpio_fops = {
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.owner = THIS_MODULE,
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.poll = gpio_poll,
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.ioctl = gpio_ioctl,
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.write = gpio_write,
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.open = gpio_open,
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.release = gpio_release,
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};
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/* main driver initialization routine, called from mem.c */
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static __init int
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gpio_init(void)
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{
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int res;
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reg_intr_vect_rw_mask intr_mask;
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/* do the formalities */
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res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
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if (res < 0) {
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printk(KERN_ERR "gpio: couldn't get a major number.\n");
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return res;
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}
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/* Clear all leds */
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LED_NETWORK_SET(0);
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LED_ACTIVE_SET(0);
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LED_DISK_READ(0);
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LED_DISK_WRITE(0);
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printk("ETRAX FS GPIO driver v2.5, (c) 2003-2005 Axis Communications AB\n");
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/* We call etrax_gpio_wake_up_check() from timer interrupt and
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* from cpu_idle() in kernel/process.c
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* The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
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* in some tests.
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*/
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if (request_irq(TIMER_INTR_VECT, gpio_poll_timer_interrupt,
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IRQF_SHARED | IRQF_DISABLED,"gpio poll", &alarmlist)) {
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printk("err: timer0 irq for gpio\n");
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}
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if (request_irq(GEN_IO_INTR_VECT, gpio_pa_interrupt,
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IRQF_SHARED | IRQF_DISABLED,"gpio PA", &alarmlist)) {
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printk("err: PA irq for gpio\n");
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}
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/* enable the gio and timer irq in global config */
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intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
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intr_mask.timer = 1;
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intr_mask.gen_io = 1;
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REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
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return res;
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}
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/* this makes sure that gpio_init is called during kernel boot */
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module_init(gpio_init);
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