215 lines
6.1 KiB
C
215 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*/
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#ifndef _CORESIGHT_TMC_H
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#define _CORESIGHT_TMC_H
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#include <linux/miscdevice.h>
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#define TMC_RSZ 0x004
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#define TMC_STS 0x00c
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#define TMC_RRD 0x010
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#define TMC_RRP 0x014
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#define TMC_RWP 0x018
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#define TMC_TRG 0x01c
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#define TMC_CTL 0x020
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#define TMC_RWD 0x024
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#define TMC_MODE 0x028
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#define TMC_LBUFLEVEL 0x02c
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#define TMC_CBUFLEVEL 0x030
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#define TMC_BUFWM 0x034
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#define TMC_RRPHI 0x038
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#define TMC_RWPHI 0x03c
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#define TMC_AXICTL 0x110
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#define TMC_DBALO 0x118
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#define TMC_DBAHI 0x11c
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#define TMC_FFSR 0x300
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#define TMC_FFCR 0x304
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#define TMC_PSCR 0x308
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#define TMC_ITMISCOP0 0xee0
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#define TMC_ITTRFLIN 0xee8
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#define TMC_ITATBDATA0 0xeec
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#define TMC_ITATBCTR2 0xef0
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#define TMC_ITATBCTR1 0xef4
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#define TMC_ITATBCTR0 0xef8
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/* register description */
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/* TMC_CTL - 0x020 */
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#define TMC_CTL_CAPT_EN BIT(0)
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/* TMC_STS - 0x00C */
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#define TMC_STS_TMCREADY_BIT 2
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#define TMC_STS_FULL BIT(0)
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#define TMC_STS_TRIGGERED BIT(1)
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/*
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* TMC_AXICTL - 0x110
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*
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* TMC AXICTL format for SoC-400
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* Bits [0-1] : ProtCtrlBit0-1
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* Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
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* Bit 6 : Reserved
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* Bit 7 : ScatterGatherMode
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* Bits [8-11] : WrBurstLen
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* Bits [12-31] : Reserved.
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* TMC AXICTL format for SoC-600, as above except:
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* Bits [2-5] : AXI WCACHE
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* Bits [16-19] : AXI RCACHE
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* Bits [20-31] : Reserved
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*/
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#define TMC_AXICTL_CLEAR_MASK 0xfbf
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#define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
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#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
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#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
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#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
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#define TMC_AXICTL_WR_BURST_16 0xF00
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/* Write-back Read and Write-allocate */
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#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
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#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
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/* TMC_FFCR - 0x304 */
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#define TMC_FFCR_FLUSHMAN_BIT 6
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#define TMC_FFCR_EN_FMT BIT(0)
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#define TMC_FFCR_EN_TI BIT(1)
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#define TMC_FFCR_FON_FLIN BIT(4)
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#define TMC_FFCR_FON_TRIG_EVT BIT(5)
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#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
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#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
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#define TMC_DEVID_NOSCAT BIT(24)
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#define TMC_DEVID_AXIAW_VALID BIT(16)
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#define TMC_DEVID_AXIAW_SHIFT 17
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#define TMC_DEVID_AXIAW_MASK 0x7f
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enum tmc_config_type {
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TMC_CONFIG_TYPE_ETB,
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TMC_CONFIG_TYPE_ETR,
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TMC_CONFIG_TYPE_ETF,
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};
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enum tmc_mode {
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TMC_MODE_CIRCULAR_BUFFER,
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TMC_MODE_SOFTWARE_FIFO,
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TMC_MODE_HARDWARE_FIFO,
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};
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enum tmc_mem_intf_width {
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TMC_MEM_INTF_WIDTH_32BITS = 1,
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TMC_MEM_INTF_WIDTH_64BITS = 2,
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TMC_MEM_INTF_WIDTH_128BITS = 4,
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TMC_MEM_INTF_WIDTH_256BITS = 8,
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};
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/* TMC ETR Capability bit definitions */
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#define TMC_ETR_SG (0x1U << 0)
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/* ETR has separate read/write cache encodings */
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#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
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/*
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* TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
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* retained when TMC leaves Disabled state, allowing us to continue
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* the tracing from a point where we stopped. This also implies that
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* the RRP/RWP/STS.Full should always be programmed to the correct
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* value. Unfortunately this is not advertised by the hardware,
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* so we have to rely on PID of the IP to detect the functionality.
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*/
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#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
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/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
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#define CORESIGHT_SOC_600_ETR_CAPS \
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(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
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/**
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* struct tmc_drvdata - specifics associated to an TMC component
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* @base: memory mapped base address for this component.
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* @dev: the device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
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* @spinlock: only one at a time pls.
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* @buf: area of memory where trace data get sent.
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* @paddr: DMA start location in RAM.
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* @vaddr: virtual representation of @paddr.
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* @size: trace buffer size.
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* @len: size of the available trace.
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* @mode: how this TMC is being used.
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* @config_type: TMC variant, must be of type @tmc_config_type.
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* @memwidth: width of the memory interface databus, in bytes.
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* @trigger_cntr: amount of words to store after a trigger.
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* @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the
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* device configuration register (DEVID)
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*/
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struct tmc_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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struct miscdevice miscdev;
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spinlock_t spinlock;
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bool reading;
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char *buf;
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dma_addr_t paddr;
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void __iomem *vaddr;
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u32 size;
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u32 len;
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u32 mode;
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enum tmc_config_type config_type;
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enum tmc_mem_intf_width memwidth;
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u32 trigger_cntr;
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u32 etr_caps;
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};
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/* Generic functions */
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void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
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void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
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void tmc_enable_hw(struct tmc_drvdata *drvdata);
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void tmc_disable_hw(struct tmc_drvdata *drvdata);
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/* ETB/ETF functions */
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int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
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int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
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extern const struct coresight_ops tmc_etb_cs_ops;
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extern const struct coresight_ops tmc_etf_cs_ops;
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/* ETR functions */
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int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
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int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
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extern const struct coresight_ops tmc_etr_cs_ops;
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#define TMC_REG_PAIR(name, lo_off, hi_off) \
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static inline u64 \
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tmc_read_##name(struct tmc_drvdata *drvdata) \
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{ \
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return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \
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} \
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static inline void \
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tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \
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{ \
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coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \
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}
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TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
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TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
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TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
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/* Initialise the caps from unadvertised static capabilities of the device */
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static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
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{
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WARN_ON(drvdata->etr_caps);
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drvdata->etr_caps = dev_caps;
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}
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static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
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{
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drvdata->etr_caps |= cap;
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}
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static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
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{
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return !!(drvdata->etr_caps & cap);
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}
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#endif
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