296 lines
9.1 KiB
C
296 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CORESIGHT_CORESIGHT_ETM_H
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#define _CORESIGHT_CORESIGHT_ETM_H
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#include <asm/local.h>
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#include <linux/spinlock.h>
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#include "coresight-priv.h"
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/*
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* Device registers:
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* 0x000 - 0x2FC: Trace registers
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* 0x300 - 0x314: Management registers
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* 0x318 - 0xEFC: Trace registers
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*
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* Coresight registers
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* 0xF00 - 0xF9C: Management registers
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* 0xFA0 - 0xFA4: Management registers in PFTv1.0
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* Trace registers in PFTv1.1
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* 0xFA8 - 0xFFC: Management registers
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*/
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/* Trace registers (0x000-0x2FC) */
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#define ETMCR 0x000
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#define ETMCCR 0x004
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#define ETMTRIGGER 0x008
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#define ETMSR 0x010
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#define ETMSCR 0x014
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#define ETMTSSCR 0x018
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#define ETMTECR2 0x01c
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#define ETMTEEVR 0x020
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#define ETMTECR1 0x024
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#define ETMFFLR 0x02c
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#define ETMACVRn(n) (0x040 + (n * 4))
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#define ETMACTRn(n) (0x080 + (n * 4))
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#define ETMCNTRLDVRn(n) (0x140 + (n * 4))
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#define ETMCNTENRn(n) (0x150 + (n * 4))
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#define ETMCNTRLDEVRn(n) (0x160 + (n * 4))
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#define ETMCNTVRn(n) (0x170 + (n * 4))
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#define ETMSQ12EVR 0x180
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#define ETMSQ21EVR 0x184
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#define ETMSQ23EVR 0x188
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#define ETMSQ31EVR 0x18c
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#define ETMSQ32EVR 0x190
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#define ETMSQ13EVR 0x194
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#define ETMSQR 0x19c
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#define ETMEXTOUTEVRn(n) (0x1a0 + (n * 4))
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#define ETMCIDCVRn(n) (0x1b0 + (n * 4))
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#define ETMCIDCMR 0x1bc
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#define ETMIMPSPEC0 0x1c0
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#define ETMIMPSPEC1 0x1c4
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#define ETMIMPSPEC2 0x1c8
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#define ETMIMPSPEC3 0x1cc
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#define ETMIMPSPEC4 0x1d0
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#define ETMIMPSPEC5 0x1d4
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#define ETMIMPSPEC6 0x1d8
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#define ETMIMPSPEC7 0x1dc
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#define ETMSYNCFR 0x1e0
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#define ETMIDR 0x1e4
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#define ETMCCER 0x1e8
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#define ETMEXTINSELR 0x1ec
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#define ETMTESSEICR 0x1f0
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#define ETMEIBCR 0x1f4
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#define ETMTSEVR 0x1f8
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#define ETMAUXCR 0x1fc
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#define ETMTRACEIDR 0x200
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#define ETMVMIDCVR 0x240
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/* Management registers (0x300-0x314) */
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#define ETMOSLAR 0x300
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#define ETMOSLSR 0x304
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#define ETMOSSRR 0x308
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#define ETMPDCR 0x310
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#define ETMPDSR 0x314
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#define ETM_MAX_ADDR_CMP 16
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#define ETM_MAX_CNTR 4
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#define ETM_MAX_CTXID_CMP 3
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/* Register definition */
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/* ETMCR - 0x00 */
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#define ETMCR_PWD_DWN BIT(0)
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#define ETMCR_STALL_MODE BIT(7)
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#define ETMCR_BRANCH_BROADCAST BIT(8)
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#define ETMCR_ETM_PRG BIT(10)
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#define ETMCR_ETM_EN BIT(11)
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#define ETMCR_CYC_ACC BIT(12)
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#define ETMCR_CTXID_SIZE (BIT(14)|BIT(15))
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#define ETMCR_TIMESTAMP_EN BIT(28)
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#define ETMCR_RETURN_STACK BIT(29)
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/* ETMCCR - 0x04 */
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#define ETMCCR_FIFOFULL BIT(23)
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/* ETMPDCR - 0x310 */
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#define ETMPDCR_PWD_UP BIT(3)
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/* ETMTECR1 - 0x024 */
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#define ETMTECR1_ADDR_COMP_1 BIT(0)
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#define ETMTECR1_INC_EXC BIT(24)
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#define ETMTECR1_START_STOP BIT(25)
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/* ETMCCER - 0x1E8 */
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#define ETMCCER_TIMESTAMP BIT(22)
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#define ETMCCER_RETSTACK BIT(23)
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#define ETM_MODE_EXCLUDE BIT(0)
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#define ETM_MODE_CYCACC BIT(1)
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#define ETM_MODE_STALL BIT(2)
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#define ETM_MODE_TIMESTAMP BIT(3)
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#define ETM_MODE_CTXID BIT(4)
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#define ETM_MODE_BBROAD BIT(5)
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#define ETM_MODE_RET_STACK BIT(6)
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#define ETM_MODE_ALL (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \
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ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \
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ETM_MODE_BBROAD | ETM_MODE_RET_STACK | \
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ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \
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ETM_MODE_EXCL_USER)
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#define ETM_SQR_MASK 0x3
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#define ETM_TRACEID_MASK 0x3f
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#define ETM_EVENT_MASK 0x1ffff
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#define ETM_SYNC_MASK 0xfff
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#define ETM_ALL_MASK 0xffffffff
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#define ETMSR_PROG_BIT 1
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#define ETM_SEQ_STATE_MAX_VAL (0x2)
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#define PORT_SIZE_MASK (GENMASK(21, 21) | GENMASK(6, 4))
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#define ETM_HARD_WIRE_RES_A /* Hard wired, always true */ \
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((0x0f << 0) | \
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/* Resource index A */ \
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(0x06 << 4))
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#define ETM_ADD_COMP_0 /* Single addr comparator 1 */ \
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((0x00 << 7) | \
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/* Resource index B */ \
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(0x00 << 11))
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#define ETM_EVENT_NOT_A BIT(14) /* NOT(A) */
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#define ETM_DEFAULT_EVENT_VAL (ETM_HARD_WIRE_RES_A | \
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ETM_ADD_COMP_0 | \
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ETM_EVENT_NOT_A)
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/**
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* struct etm_config - configuration information related to an ETM
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* @mode: controls various modes supported by this ETM/PTM.
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* @ctrl: used in conjunction with @mode.
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* @trigger_event: setting for register ETMTRIGGER.
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* @startstop_ctrl: setting for register ETMTSSCR.
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* @enable_event: setting for register ETMTEEVR.
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* @enable_ctrl1: setting for register ETMTECR1.
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* @enable_ctrl2: setting for register ETMTECR2.
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* @fifofull_level: setting for register ETMFFLR.
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* @addr_idx: index for the address comparator selection.
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* @addr_val: value for address comparator register.
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* @addr_acctype: access type for address comparator register.
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* @addr_type: current status of the comparator register.
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* @cntr_idx: index for the counter register selection.
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* @cntr_rld_val: reload value of a counter register.
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* @cntr_event: control for counter enable register.
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* @cntr_rld_event: value for counter reload event register.
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* @cntr_val: counter value register.
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* @seq_12_event: event causing the transition from 1 to 2.
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* @seq_21_event: event causing the transition from 2 to 1.
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* @seq_23_event: event causing the transition from 2 to 3.
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* @seq_31_event: event causing the transition from 3 to 1.
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* @seq_32_event: event causing the transition from 3 to 2.
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* @seq_13_event: event causing the transition from 1 to 3.
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* @seq_curr_state: current value of the sequencer register.
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* @ctxid_idx: index for the context ID registers.
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* @ctxid_pid: value for the context ID to trigger on.
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* @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise
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* the same value of ctxid_pid.
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* @ctxid_mask: mask applicable to all the context IDs.
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* @sync_freq: Synchronisation frequency.
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* @timestamp_event: Defines an event that requests the insertion
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* of a timestamp into the trace stream.
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*/
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struct etm_config {
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u32 mode;
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u32 ctrl;
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u32 trigger_event;
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u32 startstop_ctrl;
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u32 enable_event;
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u32 enable_ctrl1;
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u32 enable_ctrl2;
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u32 fifofull_level;
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u8 addr_idx;
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u32 addr_val[ETM_MAX_ADDR_CMP];
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u32 addr_acctype[ETM_MAX_ADDR_CMP];
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u32 addr_type[ETM_MAX_ADDR_CMP];
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u8 cntr_idx;
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u32 cntr_rld_val[ETM_MAX_CNTR];
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u32 cntr_event[ETM_MAX_CNTR];
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u32 cntr_rld_event[ETM_MAX_CNTR];
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u32 cntr_val[ETM_MAX_CNTR];
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u32 seq_12_event;
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u32 seq_21_event;
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u32 seq_23_event;
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u32 seq_31_event;
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u32 seq_32_event;
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u32 seq_13_event;
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u32 seq_curr_state;
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u8 ctxid_idx;
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u32 ctxid_pid[ETM_MAX_CTXID_CMP];
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u32 ctxid_vpid[ETM_MAX_CTXID_CMP];
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u32 ctxid_mask;
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u32 sync_freq;
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u32 timestamp_event;
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};
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/**
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* struct etm_drvdata - specifics associated to an ETM component
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* @base: memory mapped base address for this component.
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* @dev: the device entity associated to this component.
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* @atclk: optional clock for the core parts of the ETM.
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* @csdev: component vitals needed by the framework.
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* @spinlock: only one at a time pls.
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* @cpu: the cpu this component is affined to.
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* @port_size: port size as reported by ETMCR bit 4-6 and 21.
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* @arch: ETM/PTM version number.
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* @use_cpu14: true if management registers need to be accessed via CP14.
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* @mode: this tracer's mode, i.e sysFS, Perf or disabled.
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* @sticky_enable: true if ETM base configuration has been done.
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* @boot_enable:true if we should start tracing at boot time.
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* @os_unlock: true if access to management registers is allowed.
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* @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
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* @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
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* @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
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* @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
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* @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
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* @etmccr: value of register ETMCCR.
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* @etmccer: value of register ETMCCER.
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* @traceid: value of the current ID for this component.
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* @config: structure holding configuration parameters.
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*/
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struct etm_drvdata {
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void __iomem *base;
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struct device *dev;
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struct clk *atclk;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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int cpu;
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int port_size;
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u8 arch;
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bool use_cp14;
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local_t mode;
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bool sticky_enable;
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bool boot_enable;
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bool os_unlock;
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u8 nr_addr_cmp;
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u8 nr_cntr;
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u8 nr_ext_inp;
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u8 nr_ext_out;
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u8 nr_ctxid_cmp;
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u32 etmccr;
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u32 etmccer;
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u32 traceid;
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struct etm_config config;
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};
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static inline void etm_writel(struct etm_drvdata *drvdata,
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u32 val, u32 off)
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{
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if (drvdata->use_cp14) {
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if (etm_writel_cp14(off, val)) {
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dev_err(drvdata->dev,
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"invalid CP14 access to ETM reg: %#x", off);
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}
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} else {
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writel_relaxed(val, drvdata->base + off);
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}
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}
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static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
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{
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u32 val;
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if (drvdata->use_cp14) {
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if (etm_readl_cp14(off, &val)) {
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dev_err(drvdata->dev,
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"invalid CP14 access to ETM reg: %#x", off);
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}
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} else {
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val = readl_relaxed(drvdata->base + off);
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}
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return val;
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}
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extern const struct attribute_group *coresight_etm_groups[];
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int etm_get_trace_id(struct etm_drvdata *drvdata);
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void etm_set_default(struct etm_config *config);
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void etm_config_trace_mode(struct etm_config *config);
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struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
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#endif
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