622 lines
15 KiB
C
622 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Universal Flash Storage Host controller PCI glue driver
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*
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* Copyright (C) 2011-2013 Samsung India Software Operations
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*
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* Authors:
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* Santosh Yaraganavi <santosh.sy@samsung.com>
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* Vinayak Holikatti <h.vinayak@samsung.com>
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*/
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#include <ufs/ufshcd.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_qos.h>
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#include <linux/debugfs.h>
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#include <linux/uuid.h>
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#include <linux/acpi.h>
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#include <linux/gpio/consumer.h>
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struct ufs_host {
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void (*late_init)(struct ufs_hba *hba);
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};
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enum {
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INTEL_DSM_FNS = 0,
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INTEL_DSM_RESET = 1,
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};
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struct intel_host {
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struct ufs_host ufs_host;
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u32 dsm_fns;
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u32 active_ltr;
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u32 idle_ltr;
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struct dentry *debugfs_root;
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struct gpio_desc *reset_gpio;
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};
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static const guid_t intel_dsm_guid =
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GUID_INIT(0x1A4832A0, 0x7D03, 0x43CA,
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0xB0, 0x20, 0xF6, 0xDC, 0xD1, 0x2A, 0x19, 0x50);
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static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
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unsigned int fn, u32 *result)
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{
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union acpi_object *obj;
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int err = 0;
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size_t len;
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obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
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if (!obj)
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return -EOPNOTSUPP;
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if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
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err = -EINVAL;
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goto out;
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}
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len = min_t(size_t, obj->buffer.length, 4);
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*result = 0;
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memcpy(result, obj->buffer.pointer, len);
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out:
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ACPI_FREE(obj);
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return err;
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}
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static int intel_dsm(struct intel_host *intel_host, struct device *dev,
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unsigned int fn, u32 *result)
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{
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if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
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return -EOPNOTSUPP;
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return __intel_dsm(intel_host, dev, fn, result);
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}
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static void intel_dsm_init(struct intel_host *intel_host, struct device *dev)
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{
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int err;
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err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
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dev_dbg(dev, "DSM fns %#x, error %d\n", intel_host->dsm_fns, err);
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}
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static int ufs_intel_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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/* Cannot enable ICE until after HC enable */
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if (status == POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) {
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u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
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hce |= CRYPTO_GENERAL_ENABLE;
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ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE);
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}
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return 0;
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}
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static int ufs_intel_disable_lcc(struct ufs_hba *hba)
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{
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u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
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u32 lcc_enable = 0;
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ufshcd_dme_get(hba, attr, &lcc_enable);
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if (lcc_enable)
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ufshcd_disable_host_tx_lcc(hba);
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return 0;
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}
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static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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switch (status) {
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case PRE_CHANGE:
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err = ufs_intel_disable_lcc(hba);
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break;
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case POST_CHANGE:
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break;
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default:
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break;
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}
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return err;
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}
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static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes)
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{
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struct ufs_pa_layer_attr pwr_info = hba->pwr_info;
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int ret;
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pwr_info.lane_rx = lanes;
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pwr_info.lane_tx = lanes;
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ret = ufshcd_config_pwr_mode(hba, &pwr_info);
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if (ret)
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dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n",
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__func__, lanes, ret);
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return ret;
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}
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static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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int err = 0;
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switch (status) {
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case PRE_CHANGE:
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if (ufshcd_is_hs_mode(dev_max_params) &&
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(hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2))
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ufs_intel_set_lanes(hba, 2);
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memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params));
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break;
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case POST_CHANGE:
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if (ufshcd_is_hs_mode(dev_req_params)) {
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u32 peer_granularity;
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usleep_range(1000, 1250);
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err = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
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&peer_granularity);
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}
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break;
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default:
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break;
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}
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return err;
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}
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static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba)
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{
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u32 granularity, peer_granularity;
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u32 pa_tactivate, peer_pa_tactivate;
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int ret;
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &granularity);
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if (ret)
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goto out;
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ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &peer_granularity);
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if (ret)
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goto out;
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
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if (ret)
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goto out;
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ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &peer_pa_tactivate);
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if (ret)
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goto out;
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if (granularity == peer_granularity) {
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u32 new_peer_pa_tactivate = pa_tactivate + 2;
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ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), new_peer_pa_tactivate);
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}
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out:
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return ret;
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}
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#define INTEL_ACTIVELTR 0x804
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#define INTEL_IDLELTR 0x808
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#define INTEL_LTR_REQ BIT(15)
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#define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
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#define INTEL_LTR_SCALE_1US (2 << 10)
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#define INTEL_LTR_SCALE_32US (3 << 10)
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#define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
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static void intel_cache_ltr(struct ufs_hba *hba)
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{
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struct intel_host *host = ufshcd_get_variant(hba);
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host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
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host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
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}
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static void intel_ltr_set(struct device *dev, s32 val)
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{
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struct ufs_hba *hba = dev_get_drvdata(dev);
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struct intel_host *host = ufshcd_get_variant(hba);
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u32 ltr;
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pm_runtime_get_sync(dev);
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/*
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* Program latency tolerance (LTR) accordingly what has been asked
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* by the PM QoS layer or disable it in case we were passed
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* negative value or PM_QOS_LATENCY_ANY.
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*/
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ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
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if (val == PM_QOS_LATENCY_ANY || val < 0) {
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ltr &= ~INTEL_LTR_REQ;
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} else {
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ltr |= INTEL_LTR_REQ;
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ltr &= ~INTEL_LTR_SCALE_MASK;
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ltr &= ~INTEL_LTR_VALUE_MASK;
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if (val > INTEL_LTR_VALUE_MASK) {
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val >>= 5;
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if (val > INTEL_LTR_VALUE_MASK)
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val = INTEL_LTR_VALUE_MASK;
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ltr |= INTEL_LTR_SCALE_32US | val;
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} else {
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ltr |= INTEL_LTR_SCALE_1US | val;
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}
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}
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if (ltr == host->active_ltr)
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goto out;
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writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
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writel(ltr, hba->mmio_base + INTEL_IDLELTR);
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/* Cache the values into intel_host structure */
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intel_cache_ltr(hba);
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out:
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pm_runtime_put(dev);
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}
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static void intel_ltr_expose(struct device *dev)
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{
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dev->power.set_latency_tolerance = intel_ltr_set;
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dev_pm_qos_expose_latency_tolerance(dev);
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}
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static void intel_ltr_hide(struct device *dev)
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{
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dev_pm_qos_hide_latency_tolerance(dev);
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dev->power.set_latency_tolerance = NULL;
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}
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static void intel_add_debugfs(struct ufs_hba *hba)
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{
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struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
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struct intel_host *host = ufshcd_get_variant(hba);
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intel_cache_ltr(hba);
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host->debugfs_root = dir;
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debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
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debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
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}
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static void intel_remove_debugfs(struct ufs_hba *hba)
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{
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struct intel_host *host = ufshcd_get_variant(hba);
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debugfs_remove_recursive(host->debugfs_root);
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}
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static int ufs_intel_device_reset(struct ufs_hba *hba)
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{
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struct intel_host *host = ufshcd_get_variant(hba);
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if (host->dsm_fns & INTEL_DSM_RESET) {
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u32 result = 0;
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int err;
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err = intel_dsm(host, hba->dev, INTEL_DSM_RESET, &result);
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if (!err && !result)
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err = -EIO;
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if (err)
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dev_err(hba->dev, "%s: DSM error %d result %u\n",
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__func__, err, result);
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return err;
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}
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if (!host->reset_gpio)
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return -EOPNOTSUPP;
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gpiod_set_value_cansleep(host->reset_gpio, 1);
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usleep_range(10, 15);
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gpiod_set_value_cansleep(host->reset_gpio, 0);
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usleep_range(10, 15);
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return 0;
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}
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static struct gpio_desc *ufs_intel_get_reset_gpio(struct device *dev)
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{
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/* GPIO in _DSD has active low setting */
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return devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
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}
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static int ufs_intel_common_init(struct ufs_hba *hba)
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{
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struct intel_host *host;
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hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
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host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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ufshcd_set_variant(hba, host);
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intel_dsm_init(host, hba->dev);
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if (host->dsm_fns & INTEL_DSM_RESET) {
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if (hba->vops->device_reset)
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hba->caps |= UFSHCD_CAP_DEEPSLEEP;
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} else {
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if (hba->vops->device_reset)
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host->reset_gpio = ufs_intel_get_reset_gpio(hba->dev);
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if (IS_ERR(host->reset_gpio)) {
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dev_err(hba->dev, "%s: failed to get reset GPIO, error %ld\n",
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__func__, PTR_ERR(host->reset_gpio));
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host->reset_gpio = NULL;
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}
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if (host->reset_gpio) {
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gpiod_set_value_cansleep(host->reset_gpio, 0);
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hba->caps |= UFSHCD_CAP_DEEPSLEEP;
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}
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}
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intel_ltr_expose(hba->dev);
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intel_add_debugfs(hba);
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return 0;
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}
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static void ufs_intel_common_exit(struct ufs_hba *hba)
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{
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intel_remove_debugfs(hba);
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intel_ltr_hide(hba->dev);
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}
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static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op)
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{
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if (ufshcd_is_link_hibern8(hba)) {
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int ret = ufshcd_uic_hibern8_exit(hba);
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if (!ret) {
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ufshcd_set_link_active(hba);
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} else {
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dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
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__func__, ret);
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/*
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* Force reset and restore. Any other actions can lead
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* to an unrecoverable state.
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*/
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ufshcd_set_link_off(hba);
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}
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}
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return 0;
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}
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static int ufs_intel_ehl_init(struct ufs_hba *hba)
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{
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hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
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return ufs_intel_common_init(hba);
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}
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static void ufs_intel_lkf_late_init(struct ufs_hba *hba)
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{
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/* LKF always needs a full reset, so set PM accordingly */
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if (hba->caps & UFSHCD_CAP_DEEPSLEEP) {
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hba->spm_lvl = UFS_PM_LVL_6;
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hba->rpm_lvl = UFS_PM_LVL_6;
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} else {
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hba->spm_lvl = UFS_PM_LVL_5;
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hba->rpm_lvl = UFS_PM_LVL_5;
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}
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}
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static int ufs_intel_lkf_init(struct ufs_hba *hba)
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{
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struct ufs_host *ufs_host;
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int err;
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hba->nop_out_timeout = 200;
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hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
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hba->caps |= UFSHCD_CAP_CRYPTO;
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err = ufs_intel_common_init(hba);
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ufs_host = ufshcd_get_variant(hba);
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ufs_host->late_init = ufs_intel_lkf_late_init;
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return err;
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}
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static int ufs_intel_adl_init(struct ufs_hba *hba)
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{
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hba->nop_out_timeout = 200;
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hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
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return ufs_intel_common_init(hba);
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}
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static int ufs_intel_mtl_init(struct ufs_hba *hba)
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{
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hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN;
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return ufs_intel_common_init(hba);
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}
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static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_common_init,
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.exit = ufs_intel_common_exit,
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.link_startup_notify = ufs_intel_link_startup_notify,
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.resume = ufs_intel_resume,
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};
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static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_ehl_init,
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.exit = ufs_intel_common_exit,
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.link_startup_notify = ufs_intel_link_startup_notify,
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.resume = ufs_intel_resume,
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};
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static struct ufs_hba_variant_ops ufs_intel_lkf_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_lkf_init,
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.exit = ufs_intel_common_exit,
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.hce_enable_notify = ufs_intel_hce_enable_notify,
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.link_startup_notify = ufs_intel_link_startup_notify,
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.pwr_change_notify = ufs_intel_lkf_pwr_change_notify,
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.apply_dev_quirks = ufs_intel_lkf_apply_dev_quirks,
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.resume = ufs_intel_resume,
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.device_reset = ufs_intel_device_reset,
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};
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static struct ufs_hba_variant_ops ufs_intel_adl_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_adl_init,
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.exit = ufs_intel_common_exit,
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.link_startup_notify = ufs_intel_link_startup_notify,
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.resume = ufs_intel_resume,
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.device_reset = ufs_intel_device_reset,
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};
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static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
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.name = "intel-pci",
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.init = ufs_intel_mtl_init,
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.exit = ufs_intel_common_exit,
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.hce_enable_notify = ufs_intel_hce_enable_notify,
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.link_startup_notify = ufs_intel_link_startup_notify,
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|
.resume = ufs_intel_resume,
|
|
.device_reset = ufs_intel_device_reset,
|
|
};
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int ufshcd_pci_restore(struct device *dev)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
|
|
/* Force a full reset and restore */
|
|
ufshcd_set_link_off(hba);
|
|
|
|
return ufshcd_system_resume(dev);
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* ufshcd_pci_shutdown - main function to put the controller in reset state
|
|
* @pdev: pointer to PCI device handle
|
|
*/
|
|
static void ufshcd_pci_shutdown(struct pci_dev *pdev)
|
|
{
|
|
ufshcd_shutdown((struct ufs_hba *)pci_get_drvdata(pdev));
|
|
}
|
|
|
|
/**
|
|
* ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
|
|
* data structure memory
|
|
* @pdev: pointer to PCI handle
|
|
*/
|
|
static void ufshcd_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct ufs_hba *hba = pci_get_drvdata(pdev);
|
|
|
|
pm_runtime_forbid(&pdev->dev);
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
ufshcd_remove(hba);
|
|
ufshcd_dealloc_host(hba);
|
|
}
|
|
|
|
/**
|
|
* ufshcd_pci_probe - probe routine of the driver
|
|
* @pdev: pointer to PCI device handle
|
|
* @id: PCI device id
|
|
*
|
|
* Returns 0 on success, non-zero value on failure
|
|
*/
|
|
static int
|
|
ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
struct ufs_host *ufs_host;
|
|
struct ufs_hba *hba;
|
|
void __iomem *mmio_base;
|
|
int err;
|
|
|
|
err = pcim_enable_device(pdev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "pcim_enable_device failed\n");
|
|
return err;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "request and iomap failed\n");
|
|
return err;
|
|
}
|
|
|
|
mmio_base = pcim_iomap_table(pdev)[0];
|
|
|
|
err = ufshcd_alloc_host(&pdev->dev, &hba);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Allocation failed\n");
|
|
return err;
|
|
}
|
|
|
|
hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
|
|
|
|
err = ufshcd_init(hba, mmio_base, pdev->irq);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Initialization failed\n");
|
|
ufshcd_dealloc_host(hba);
|
|
return err;
|
|
}
|
|
|
|
ufs_host = ufshcd_get_variant(hba);
|
|
if (ufs_host && ufs_host->late_init)
|
|
ufs_host->late_init(hba);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops ufshcd_pci_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
|
|
#ifdef CONFIG_PM_SLEEP
|
|
.suspend = ufshcd_system_suspend,
|
|
.resume = ufshcd_system_resume,
|
|
.freeze = ufshcd_system_suspend,
|
|
.thaw = ufshcd_system_resume,
|
|
.poweroff = ufshcd_system_suspend,
|
|
.restore = ufshcd_pci_restore,
|
|
.prepare = ufshcd_suspend_prepare,
|
|
.complete = ufshcd_resume_complete,
|
|
#endif
|
|
};
|
|
|
|
static const struct pci_device_id ufshcd_pci_tbl[] = {
|
|
{ PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
|
|
{ PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
|
|
{ PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
|
|
{ PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
|
|
{ PCI_VDEVICE(INTEL, 0x98FA), (kernel_ulong_t)&ufs_intel_lkf_hba_vops },
|
|
{ PCI_VDEVICE(INTEL, 0x51FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops },
|
|
{ PCI_VDEVICE(INTEL, 0x54FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops },
|
|
{ PCI_VDEVICE(INTEL, 0x7E47), (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
|
|
{ } /* terminate list */
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
|
|
|
|
static struct pci_driver ufshcd_pci_driver = {
|
|
.name = UFSHCD,
|
|
.id_table = ufshcd_pci_tbl,
|
|
.probe = ufshcd_pci_probe,
|
|
.remove = ufshcd_pci_remove,
|
|
.shutdown = ufshcd_pci_shutdown,
|
|
.driver = {
|
|
.pm = &ufshcd_pci_pm_ops
|
|
},
|
|
};
|
|
|
|
module_pci_driver(ufshcd_pci_driver);
|
|
|
|
MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
|
|
MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
|
|
MODULE_DESCRIPTION("UFS host controller PCI glue driver");
|
|
MODULE_LICENSE("GPL");
|