154 lines
7.1 KiB
Plaintext
154 lines
7.1 KiB
Plaintext
PXA/MMP - DMA Slave controller
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==============================
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Constraints
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-----------
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a) Transfers hot queuing
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A driver submitting a transfer and issuing it should be granted the transfer
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is queued even on a running DMA channel.
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This implies that the queuing doesn't wait for the previous transfer end,
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and that the descriptor chaining is not only done in the irq/tasklet code
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triggered by the end of the transfer.
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A transfer which is submitted and issued on a phy doesn't wait for a phy to
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stop and restart, but is submitted on a "running channel". The other
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drivers, especially mmp_pdma waited for the phy to stop before relaunching
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a new transfer.
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b) All transfers having asked for confirmation should be signaled
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Any issued transfer with DMA_PREP_INTERRUPT should trigger a callback call.
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This implies that even if an irq/tasklet is triggered by end of tx1, but
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at the time of irq/dma tx2 is already finished, tx1->complete() and
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tx2->complete() should be called.
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c) Channel running state
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A driver should be able to query if a channel is running or not. For the
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multimedia case, such as video capture, if a transfer is submitted and then
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a check of the DMA channel reports a "stopped channel", the transfer should
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not be issued until the next "start of frame interrupt", hence the need to
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know if a channel is in running or stopped state.
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d) Bandwidth guarantee
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The PXA architecture has 4 levels of DMAs priorities : high, normal, low.
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The high prorities get twice as much bandwidth as the normal, which get twice
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as much as the low priorities.
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A driver should be able to request a priority, especially the real-time
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ones such as pxa_camera with (big) throughputs.
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Design
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------
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a) Virtual channels
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Same concept as in sa11x0 driver, ie. a driver was assigned a "virtual
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channel" linked to the requestor line, and the physical DMA channel is
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assigned on the fly when the transfer is issued.
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b) Transfer anatomy for a scatter-gather transfer
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+------------+-----+---------------+----------------+-----------------+
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| desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
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+------------+-----+---------------+----------------+-----------------+
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This structure is pointed by dma->sg_cpu.
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The descriptors are used as follows :
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- desc-sg[i]: i-th descriptor, transferring the i-th sg
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element to the video buffer scatter gather
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- status updater
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Transfers a single u32 to a well known dma coherent memory to leave
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a trace that this transfer is done. The "well known" is unique per
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physical channel, meaning that a read of this value will tell which
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is the last finished transfer at that point in time.
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- finisher: has ddadr=DADDR_STOP, dcmd=ENDIRQEN
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- linker: has ddadr= desc-sg[0] of next transfer, dcmd=0
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c) Transfers hot-chaining
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Suppose the running chain is :
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Buffer 1 Buffer 2
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+---------+----+---+ +----+----+----+---+
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| d0 | .. | dN | l | | d0 | .. | dN | f |
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+---------+----+-|-+ ^----+----+----+---+
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+----+
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After a call to dmaengine_submit(b3), the chain will look like :
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Buffer 1 Buffer 2 Buffer 3
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+---------+----+---+ +----+----+----+---+ +----+----+----+---+
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| d0 | .. | dN | l | | d0 | .. | dN | l | | d0 | .. | dN | f |
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+---------+----+-|-+ ^----+----+----+-|-+ ^----+----+----+---+
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| | | |
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+----+ +----+
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new_link
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If while new_link was created the DMA channel stopped, it is _not_
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restarted. Hot-chaining doesn't break the assumption that
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dma_async_issue_pending() is to be used to ensure the transfer is actually started.
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One exception to this rule :
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- if Buffer1 and Buffer2 had all their addresses 8 bytes aligned
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- and if Buffer3 has at least one address not 4 bytes aligned
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- then hot-chaining cannot happen, as the channel must be stopped, the
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"align bit" must be set, and the channel restarted As a consequence,
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such a transfer tx_submit() will be queued on the submitted queue, and
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this specific case if the DMA is already running in aligned mode.
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d) Transfers completion updater
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Each time a transfer is completed on a channel, an interrupt might be
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generated or not, up to the client's request. But in each case, the last
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descriptor of a transfer, the "status updater", will write the latest
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transfer being completed into the physical channel's completion mark.
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This will speed up residue calculation, for large transfers such as video
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buffers which hold around 6k descriptors or more. This also allows without
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any lock to find out what is the latest completed transfer in a running
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DMA chain.
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e) Transfers completion, irq and tasklet
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When a transfer flagged as "DMA_PREP_INTERRUPT" is finished, the dma irq
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is raised. Upon this interrupt, a tasklet is scheduled for the physical
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channel.
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The tasklet is responsible for :
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- reading the physical channel last updater mark
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- calling all the transfer callbacks of finished transfers, based on
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that mark, and each transfer flags.
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If a transfer is completed while this handling is done, a dma irq will
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be raised, and the tasklet will be scheduled once again, having a new
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updater mark.
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f) Residue
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Residue granularity will be descriptor based. The issued but not completed
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transfers will be scanned for all of their descriptors against the
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currently running descriptor.
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g) Most complicated case of driver's tx queues
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The most tricky situation is when :
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- there are not "acked" transfers (tx0)
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- a driver submitted an aligned tx1, not chained
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- a driver submitted an aligned tx2 => tx2 is cold chained to tx1
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- a driver issued tx1+tx2 => channel is running in aligned mode
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- a driver submitted an aligned tx3 => tx3 is hot-chained
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- a driver submitted an unaligned tx4 => tx4 is put in submitted queue,
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not chained
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- a driver issued tx4 => tx4 is put in issued queue, not chained
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- a driver submitted an aligned tx5 => tx5 is put in submitted queue, not
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chained
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- a driver submitted an aligned tx6 => tx6 is put in submitted queue,
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cold chained to tx5
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This translates into (after tx4 is issued) :
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- issued queue
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+-----+ +-----+ +-----+ +-----+
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| tx1 | | tx2 | | tx3 | | tx4 |
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+---|-+ ^---|-+ ^-----+ +-----+
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| | | |
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+---+ +---+
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- submitted queue
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+-----+ +-----+
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| tx5 | | tx6 |
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+---|-+ ^-----+
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+---+
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- completed queue : empty
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- allocated queue : tx0
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It should be noted that after tx3 is completed, the channel is stopped, and
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restarted in "unaligned mode" to handle tx4.
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Author: Robert Jarzmik <robert.jarzmik@free.fr>
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