88 lines
1.7 KiB
Plaintext
88 lines
1.7 KiB
Plaintext
/dts-v1/;
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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/ {
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model = "Qualcomm MSM8660";
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02080000 0x1000 >,
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< 0x02081000 0x1000 >;
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};
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timer@2000000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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msmgpio: gpio@800000 {
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compatible = "qcom,msm-gpio";
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reg = <0x00800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpio = <173>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8660";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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};
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serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 0x0>;
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clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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};
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