Leonid Yegoshin a168b8f1cd MIPS: mm: Add MIPS R6 instruction encodings ... MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>		2015-02-16 14:02:50 +00:00
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asm	MIPS: mm: Add MIPS R6 instruction encodings	2015-02-16 14:02:50 +00:00