760 lines
25 KiB
C
760 lines
25 KiB
C
/*
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* Contains CPU feature definitions
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "CPU features: " fmt
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#include <linux/bsearch.h>
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#include <linux/sort.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cpufeature.h>
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#include <asm/processor.h>
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#include <asm/sysreg.h>
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static bool mixed_endian_el0 = true;
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unsigned long elf_hwcap __read_mostly;
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EXPORT_SYMBOL_GPL(elf_hwcap);
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#ifdef CONFIG_COMPAT
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#define COMPAT_ELF_HWCAP_DEFAULT \
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(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
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COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
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COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
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COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
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COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
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COMPAT_HWCAP_LPAE)
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unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
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unsigned int compat_elf_hwcap2 __read_mostly;
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#endif
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DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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bool cpu_supports_mixed_endian_el0(void)
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{
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return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
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}
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bool system_supports_mixed_endian_el0(void)
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{
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return mixed_endian_el0;
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}
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static void update_mixed_endian_el0_support(struct cpuinfo_arm64 *info)
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{
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mixed_endian_el0 &= id_aa64mmfr0_mixed_endian_el0(info->reg_id_aa64mmfr0);
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}
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#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
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{ \
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.strict = STRICT, \
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.type = TYPE, \
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.shift = SHIFT, \
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.width = WIDTH, \
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.safe_val = SAFE_VAL, \
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}
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#define ARM64_FTR_END \
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{ \
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.width = 0, \
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}
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static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
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/* Linux doesn't care about the EL3 */
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ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
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/* Linux shouldn't care about secure memory */
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ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
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/*
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* Differing PARange is fine as long as all peripherals and memory are mapped
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* within the minimum PARange of all CPUs
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*/
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ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_ctr[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
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/*
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* Linux can handle differing I-cache policies. Userspace JITs will
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* make use of *minLine
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*/
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ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_mmfr0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
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ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_mvfr2[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_dczid[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_isar5[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_mmfr4[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_id_pfr0[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
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ARM64_FTR_END,
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};
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/*
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* Common ftr bits for a 32bit register with all hidden, strict
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* attributes, with 4bit feature fields and a default safe value of
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* 0. Covers the following 32bit registers:
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* id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
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*/
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static struct arm64_ftr_bits ftr_generic_32bits[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
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ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_generic[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_generic32[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
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ARM64_FTR_END,
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};
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static struct arm64_ftr_bits ftr_aa64raz[] = {
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ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
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ARM64_FTR_END,
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};
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#define ARM64_FTR_REG(id, table) \
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{ \
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.sys_id = id, \
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.name = #id, \
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.ftr_bits = &((table)[0]), \
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}
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static struct arm64_ftr_reg arm64_ftr_regs[] = {
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/* Op1 = 0, CRn = 0, CRm = 1 */
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ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
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ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
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ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
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/* Op1 = 0, CRn = 0, CRm = 2 */
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ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
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ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
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/* Op1 = 0, CRn = 0, CRm = 3 */
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ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
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ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
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/* Op1 = 0, CRn = 0, CRm = 4 */
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ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
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ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
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/* Op1 = 0, CRn = 0, CRm = 5 */
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ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
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ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
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/* Op1 = 0, CRn = 0, CRm = 6 */
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ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
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ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
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/* Op1 = 0, CRn = 0, CRm = 7 */
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ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
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ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
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/* Op1 = 3, CRn = 0, CRm = 0 */
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ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
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ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
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/* Op1 = 3, CRn = 14, CRm = 0 */
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ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
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};
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static int search_cmp_ftr_reg(const void *id, const void *regp)
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{
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return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
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}
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/*
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* get_arm64_ftr_reg - Lookup a feature register entry using its
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* sys_reg() encoding. With the array arm64_ftr_regs sorted in the
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* ascending order of sys_id , we use binary search to find a matching
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* entry.
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*
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* returns - Upon success, matching ftr_reg entry for id.
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* - NULL on failure. It is upto the caller to decide
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* the impact of a failure.
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*/
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static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
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{
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return bsearch((const void *)(unsigned long)sys_id,
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arm64_ftr_regs,
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ARRAY_SIZE(arm64_ftr_regs),
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sizeof(arm64_ftr_regs[0]),
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search_cmp_ftr_reg);
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}
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static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
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{
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u64 mask = arm64_ftr_mask(ftrp);
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reg &= ~mask;
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reg |= (ftr_val << ftrp->shift) & mask;
|
|
return reg;
|
|
}
|
|
|
|
static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
|
|
{
|
|
s64 ret = 0;
|
|
|
|
switch (ftrp->type) {
|
|
case FTR_EXACT:
|
|
ret = ftrp->safe_val;
|
|
break;
|
|
case FTR_LOWER_SAFE:
|
|
ret = new < cur ? new : cur;
|
|
break;
|
|
case FTR_HIGHER_SAFE:
|
|
ret = new > cur ? new : cur;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init sort_cmp_ftr_regs(const void *a, const void *b)
|
|
{
|
|
return ((const struct arm64_ftr_reg *)a)->sys_id -
|
|
((const struct arm64_ftr_reg *)b)->sys_id;
|
|
}
|
|
|
|
static void __init swap_ftr_regs(void *a, void *b, int size)
|
|
{
|
|
struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
|
|
*(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
|
|
*(struct arm64_ftr_reg *)b = tmp;
|
|
}
|
|
|
|
static void __init sort_ftr_regs(void)
|
|
{
|
|
/* Keep the array sorted so that we can do the binary search */
|
|
sort(arm64_ftr_regs,
|
|
ARRAY_SIZE(arm64_ftr_regs),
|
|
sizeof(arm64_ftr_regs[0]),
|
|
sort_cmp_ftr_regs,
|
|
swap_ftr_regs);
|
|
}
|
|
|
|
/*
|
|
* Initialise the CPU feature register from Boot CPU values.
|
|
* Also initiliases the strict_mask for the register.
|
|
*/
|
|
static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
|
|
{
|
|
u64 val = 0;
|
|
u64 strict_mask = ~0x0ULL;
|
|
struct arm64_ftr_bits *ftrp;
|
|
struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
|
|
|
|
BUG_ON(!reg);
|
|
|
|
for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
|
|
s64 ftr_new = arm64_ftr_value(ftrp, new);
|
|
|
|
val = arm64_ftr_set_value(ftrp, val, ftr_new);
|
|
if (!ftrp->strict)
|
|
strict_mask &= ~arm64_ftr_mask(ftrp);
|
|
}
|
|
reg->sys_val = val;
|
|
reg->strict_mask = strict_mask;
|
|
}
|
|
|
|
void __init init_cpu_features(struct cpuinfo_arm64 *info)
|
|
{
|
|
/* Before we start using the tables, make sure it is sorted */
|
|
sort_ftr_regs();
|
|
|
|
init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
|
|
init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
|
|
init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
|
|
init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
|
|
init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
|
|
init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
|
|
init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
|
|
init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
|
|
init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
|
|
init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
|
|
init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
|
|
init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
|
|
init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
|
|
init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
|
|
init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
|
|
init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
|
|
init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
|
|
init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
|
|
init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
|
|
init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
|
|
init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
|
|
init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
|
|
init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
|
|
init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
|
|
init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
|
|
init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
|
|
init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
|
|
|
|
/* This will be removed later, once we start using the infrastructure */
|
|
update_mixed_endian_el0_support(info);
|
|
}
|
|
|
|
static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
|
|
{
|
|
struct arm64_ftr_bits *ftrp;
|
|
|
|
for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
|
|
s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
|
|
s64 ftr_new = arm64_ftr_value(ftrp, new);
|
|
|
|
if (ftr_cur == ftr_new)
|
|
continue;
|
|
/* Find a safe value */
|
|
ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
|
|
reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
|
|
}
|
|
|
|
}
|
|
|
|
static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
|
|
{
|
|
struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
|
|
|
|
BUG_ON(!regp);
|
|
update_cpu_ftr_reg(regp, val);
|
|
if ((boot & regp->strict_mask) == (val & regp->strict_mask))
|
|
return 0;
|
|
pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
|
|
regp->name, boot, cpu, val);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Update system wide CPU feature registers with the values from a
|
|
* non-boot CPU. Also performs SANITY checks to make sure that there
|
|
* aren't any insane variations from that of the boot CPU.
|
|
*/
|
|
void update_cpu_features(int cpu,
|
|
struct cpuinfo_arm64 *info,
|
|
struct cpuinfo_arm64 *boot)
|
|
{
|
|
int taint = 0;
|
|
|
|
/*
|
|
* The kernel can handle differing I-cache policies, but otherwise
|
|
* caches should look identical. Userspace JITs will make use of
|
|
* *minLine.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
|
|
info->reg_ctr, boot->reg_ctr);
|
|
|
|
/*
|
|
* Userspace may perform DC ZVA instructions. Mismatched block sizes
|
|
* could result in too much or too little memory being zeroed if a
|
|
* process is preempted and migrated between CPUs.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
|
|
info->reg_dczid, boot->reg_dczid);
|
|
|
|
/* If different, timekeeping will be broken (especially with KVM) */
|
|
taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
|
|
info->reg_cntfrq, boot->reg_cntfrq);
|
|
|
|
/*
|
|
* The kernel uses self-hosted debug features and expects CPUs to
|
|
* support identical debug features. We presently need CTX_CMPs, WRPs,
|
|
* and BRPs to be identical.
|
|
* ID_AA64DFR1 is currently RES0.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
|
|
info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
|
|
info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
|
|
/*
|
|
* Even in big.LITTLE, processors should be identical instruction-set
|
|
* wise.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
|
|
info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
|
|
info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
|
|
|
|
/*
|
|
* Differing PARange support is fine as long as all peripherals and
|
|
* memory are mapped within the minimum PARange of all CPUs.
|
|
* Linux should not care about secure memory.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
|
|
info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
|
|
info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
|
|
|
|
/*
|
|
* EL3 is not our concern.
|
|
* ID_AA64PFR1 is currently RES0.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
|
|
info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
|
|
taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
|
|
info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
|
|
|
|
/*
|
|
* If we have AArch32, we care about 32-bit features for compat. These
|
|
* registers should be RES0 otherwise.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
|
|
info->reg_id_dfr0, boot->reg_id_dfr0);
|
|
taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
|
|
info->reg_id_isar0, boot->reg_id_isar0);
|
|
taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
|
|
info->reg_id_isar1, boot->reg_id_isar1);
|
|
taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
|
|
info->reg_id_isar2, boot->reg_id_isar2);
|
|
taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
|
|
info->reg_id_isar3, boot->reg_id_isar3);
|
|
taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
|
|
info->reg_id_isar4, boot->reg_id_isar4);
|
|
taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
|
|
info->reg_id_isar5, boot->reg_id_isar5);
|
|
|
|
/*
|
|
* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
|
|
* ACTLR formats could differ across CPUs and therefore would have to
|
|
* be trapped for virtualization anyway.
|
|
*/
|
|
taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
|
|
info->reg_id_mmfr0, boot->reg_id_mmfr0);
|
|
taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
|
|
info->reg_id_mmfr1, boot->reg_id_mmfr1);
|
|
taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
|
|
info->reg_id_mmfr2, boot->reg_id_mmfr2);
|
|
taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
|
|
info->reg_id_mmfr3, boot->reg_id_mmfr3);
|
|
taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
|
|
info->reg_id_pfr0, boot->reg_id_pfr0);
|
|
taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
|
|
info->reg_id_pfr1, boot->reg_id_pfr1);
|
|
taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
|
|
info->reg_mvfr0, boot->reg_mvfr0);
|
|
taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
|
|
info->reg_mvfr1, boot->reg_mvfr1);
|
|
taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
|
|
info->reg_mvfr2, boot->reg_mvfr2);
|
|
|
|
/*
|
|
* Mismatched CPU features are a recipe for disaster. Don't even
|
|
* pretend to support them.
|
|
*/
|
|
WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
|
|
"Unsupported CPU feature variation.\n");
|
|
|
|
update_mixed_endian_el0_support(info);
|
|
}
|
|
|
|
static bool
|
|
feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
|
|
{
|
|
int val = cpuid_feature_extract_field(reg, entry->field_pos);
|
|
|
|
return val >= entry->min_field_value;
|
|
}
|
|
|
|
#define __ID_FEAT_CHK(reg) \
|
|
static bool __maybe_unused \
|
|
has_##reg##_feature(const struct arm64_cpu_capabilities *entry) \
|
|
{ \
|
|
u64 val; \
|
|
\
|
|
val = read_cpuid(reg##_el1); \
|
|
return feature_matches(val, entry); \
|
|
}
|
|
|
|
__ID_FEAT_CHK(id_aa64pfr0);
|
|
__ID_FEAT_CHK(id_aa64mmfr1);
|
|
__ID_FEAT_CHK(id_aa64isar0);
|
|
|
|
static const struct arm64_cpu_capabilities arm64_features[] = {
|
|
{
|
|
.desc = "GIC system register CPU interface",
|
|
.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
|
|
.matches = has_id_aa64pfr0_feature,
|
|
.field_pos = 24,
|
|
.min_field_value = 1,
|
|
},
|
|
#ifdef CONFIG_ARM64_PAN
|
|
{
|
|
.desc = "Privileged Access Never",
|
|
.capability = ARM64_HAS_PAN,
|
|
.matches = has_id_aa64mmfr1_feature,
|
|
.field_pos = 20,
|
|
.min_field_value = 1,
|
|
.enable = cpu_enable_pan,
|
|
},
|
|
#endif /* CONFIG_ARM64_PAN */
|
|
#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
|
|
{
|
|
.desc = "LSE atomic instructions",
|
|
.capability = ARM64_HAS_LSE_ATOMICS,
|
|
.matches = has_id_aa64isar0_feature,
|
|
.field_pos = 20,
|
|
.min_field_value = 2,
|
|
},
|
|
#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
|
|
{},
|
|
};
|
|
|
|
void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
|
|
const char *info)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; caps[i].desc; i++) {
|
|
if (!caps[i].matches(&caps[i]))
|
|
continue;
|
|
|
|
if (!cpus_have_cap(caps[i].capability))
|
|
pr_info("%s %s\n", info, caps[i].desc);
|
|
cpus_set_cap(caps[i].capability);
|
|
}
|
|
|
|
/* second pass allows enable() to consider interacting capabilities */
|
|
for (i = 0; caps[i].desc; i++) {
|
|
if (cpus_have_cap(caps[i].capability) && caps[i].enable)
|
|
caps[i].enable();
|
|
}
|
|
}
|
|
|
|
void check_local_cpu_features(void)
|
|
{
|
|
check_cpu_capabilities(arm64_features, "detected feature:");
|
|
}
|
|
|
|
void __init setup_cpu_features(void)
|
|
{
|
|
u64 features;
|
|
s64 block;
|
|
u32 cwg;
|
|
int cls;
|
|
|
|
/*
|
|
* Check for sane CTR_EL0.CWG value.
|
|
*/
|
|
cwg = cache_type_cwg();
|
|
cls = cache_line_size();
|
|
if (!cwg)
|
|
pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
|
|
cls);
|
|
if (L1_CACHE_BYTES < cls)
|
|
pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
|
|
L1_CACHE_BYTES, cls);
|
|
|
|
/*
|
|
* ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
|
|
* The blocks we test below represent incremental functionality
|
|
* for non-negative values. Negative values are reserved.
|
|
*/
|
|
features = read_cpuid(ID_AA64ISAR0_EL1);
|
|
block = cpuid_feature_extract_field(features, 4);
|
|
if (block > 0) {
|
|
switch (block) {
|
|
default:
|
|
case 2:
|
|
elf_hwcap |= HWCAP_PMULL;
|
|
case 1:
|
|
elf_hwcap |= HWCAP_AES;
|
|
case 0:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (cpuid_feature_extract_field(features, 8) > 0)
|
|
elf_hwcap |= HWCAP_SHA1;
|
|
|
|
if (cpuid_feature_extract_field(features, 12) > 0)
|
|
elf_hwcap |= HWCAP_SHA2;
|
|
|
|
if (cpuid_feature_extract_field(features, 16) > 0)
|
|
elf_hwcap |= HWCAP_CRC32;
|
|
|
|
block = cpuid_feature_extract_field(features, 20);
|
|
if (block > 0) {
|
|
switch (block) {
|
|
default:
|
|
case 2:
|
|
elf_hwcap |= HWCAP_ATOMICS;
|
|
case 1:
|
|
/* RESERVED */
|
|
case 0:
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
/*
|
|
* ID_ISAR5_EL1 carries similar information as above, but pertaining to
|
|
* the AArch32 32-bit execution state.
|
|
*/
|
|
features = read_cpuid(ID_ISAR5_EL1);
|
|
block = cpuid_feature_extract_field(features, 4);
|
|
if (block > 0) {
|
|
switch (block) {
|
|
default:
|
|
case 2:
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
|
|
case 1:
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
|
|
case 0:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (cpuid_feature_extract_field(features, 8) > 0)
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
|
|
|
|
if (cpuid_feature_extract_field(features, 12) > 0)
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
|
|
|
|
if (cpuid_feature_extract_field(features, 16) > 0)
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
|
|
#endif
|
|
}
|