525 lines
16 KiB
C
525 lines
16 KiB
C
/*
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* Copyright 2003 NVIDIA, Corporation
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* Copyright 2006 Dave Airlie
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* Copyright 2007 Maarten Maathuis
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm_crtc_helper.h"
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#include "nouveau_drv.h"
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#include "nouveau_encoder.h"
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#include "nouveau_connector.h"
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#include "nouveau_crtc.h"
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#include "nouveau_hw.h"
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#include "nvreg.h"
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int nv04_dac_output_offset(struct drm_encoder *encoder)
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{
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struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
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int offset = 0;
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if (dcb->or & (8 | OUTPUT_C))
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offset += 0x68;
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if (dcb->or & (8 | OUTPUT_B))
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offset += 0x2000;
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return offset;
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}
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/*
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* arbitrary limit to number of sense oscillations tolerated in one sample
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* period (observed to be at least 13 in "nvidia")
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*/
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#define MAX_HBLANK_OSC 20
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/*
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* arbitrary limit to number of conflicting sample pairs to tolerate at a
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* voltage step (observed to be at least 5 in "nvidia")
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*/
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#define MAX_SAMPLE_PAIRS 10
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static int sample_load_twice(struct drm_device *dev, bool sense[2])
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{
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int i;
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for (i = 0; i < 2; i++) {
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bool sense_a, sense_b, sense_b_prime;
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int j = 0;
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/*
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* wait for bit 0 clear -- out of hblank -- (say reg value 0x4),
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* then wait for transition 0x4->0x5->0x4: enter hblank, leave
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* hblank again
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* use a 10ms timeout (guards against crtc being inactive, in
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* which case blank state would never change)
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*/
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if (!nouveau_wait_until(dev, 10000000, NV_PRMCIO_INP0__COLOR,
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0x00000001, 0x00000000))
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return -EBUSY;
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if (!nouveau_wait_until(dev, 10000000, NV_PRMCIO_INP0__COLOR,
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0x00000001, 0x00000001))
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return -EBUSY;
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if (!nouveau_wait_until(dev, 10000000, NV_PRMCIO_INP0__COLOR,
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0x00000001, 0x00000000))
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return -EBUSY;
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udelay(100);
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/* when level triggers, sense is _LO_ */
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sense_a = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
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/* take another reading until it agrees with sense_a... */
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do {
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udelay(100);
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sense_b = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
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if (sense_a != sense_b) {
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sense_b_prime =
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nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
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if (sense_b == sense_b_prime) {
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/* ... unless two consecutive subsequent
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* samples agree; sense_a is replaced */
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sense_a = sense_b;
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/* force mis-match so we loop */
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sense_b = !sense_a;
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}
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}
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} while ((sense_a != sense_b) && ++j < MAX_HBLANK_OSC);
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if (j == MAX_HBLANK_OSC)
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/* with so much oscillation, default to sense:LO */
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sense[i] = false;
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else
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sense[i] = sense_a;
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}
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return 0;
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}
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static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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uint8_t saved_seq1, saved_pi, saved_rpc1;
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uint8_t saved_palette0[3], saved_palette_mask;
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uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
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int i;
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uint8_t blue;
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bool sense = true;
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/*
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* for this detection to work, there needs to be a mode set up on the
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* CRTC. this is presumed to be the case
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*/
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if (nv_two_heads(dev))
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/* only implemented for head A for now */
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NVSetOwner(dev, 0);
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saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
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NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
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saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL,
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saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
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msleep(10);
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saved_pi = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX,
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saved_pi & ~(0x80 | MASK(NV_CIO_CRE_PIXEL_FORMAT)));
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saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
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nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
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for (i = 0; i < 3; i++)
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saved_palette0[i] = nv_rd08(dev, NV_PRMDIO_PALETTE_DATA);
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saved_palette_mask = nv_rd08(dev, NV_PRMDIO_PIXEL_MASK);
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nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, 0);
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saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,
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(saved_rgen_ctrl & ~(NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
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NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM)) |
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NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON);
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blue = 8; /* start of test range */
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do {
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bool sense_pair[2];
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nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
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nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0);
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nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0);
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/* testing blue won't find monochrome monitors. I don't care */
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nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, blue);
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i = 0;
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/* take sample pairs until both samples in the pair agree */
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do {
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if (sample_load_twice(dev, sense_pair))
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goto out;
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} while ((sense_pair[0] != sense_pair[1]) &&
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++i < MAX_SAMPLE_PAIRS);
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if (i == MAX_SAMPLE_PAIRS)
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/* too much oscillation defaults to LO */
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sense = false;
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else
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sense = sense_pair[0];
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/*
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* if sense goes LO before blue ramps to 0x18, monitor is not connected.
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* ergo, if blue gets to 0x18, monitor must be connected
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*/
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} while (++blue < 0x18 && sense);
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out:
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nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);
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nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
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for (i = 0; i < 3; i++)
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nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
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NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
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if (blue == 0x18) {
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NV_INFO(dev, "Load detected on head A\n");
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return connector_status_connected;
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}
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return connector_status_disconnected;
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}
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enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
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uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
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uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
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saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
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int head, present = 0;
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#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
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if (dcb->type == OUTPUT_TV) {
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testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0);
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if (dev_priv->vbios->tvdactestval)
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testval = dev_priv->vbios->tvdactestval;
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} else {
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testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
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if (dev_priv->vbios->dactestval)
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testval = dev_priv->vbios->dactestval;
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}
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saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
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saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
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saved_powerctrl_2 = nvReadMC(dev, NV_PBUS_POWERCTRL_2);
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nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
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if (regoffset == 0x68) {
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saved_powerctrl_4 = nvReadMC(dev, NV_PBUS_POWERCTRL_4);
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nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
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}
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saved_gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
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saved_gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
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nv17_gpio_set(dev, DCB_GPIO_TVDAC1, dcb->type == OUTPUT_TV);
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nv17_gpio_set(dev, DCB_GPIO_TVDAC0, dcb->type == OUTPUT_TV);
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msleep(4);
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saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
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head = (saved_routput & 0x100) >> 8;
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#if 0
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/* if there's a spare crtc, using it will minimise flicker for the case
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* where the in-use crtc is in use by an off-chip tmds encoder */
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if (xf86_config->crtc[head]->enabled && !xf86_config->crtc[head ^ 1]->enabled)
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head ^= 1;
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#endif
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/* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
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routput = (saved_routput & 0xfffffece) | head << 8;
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if (dev_priv->card_type >= NV_40) {
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if (dcb->type == OUTPUT_TV)
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routput |= 0x1a << 16;
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else
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routput &= ~(0x1a << 16);
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}
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput);
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msleep(1);
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temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, temp | 1);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA,
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NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK | testval);
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temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
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temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
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msleep(5);
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temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
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if (dcb->type == OUTPUT_TV)
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present = (nv17_tv_detect(encoder, connector, temp)
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== connector_status_connected);
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else
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present = temp & NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI;
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temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
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temp & ~NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA, 0);
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/* bios does something more complex for restoring, but I think this is good enough */
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
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if (regoffset == 0x68)
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nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
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nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
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nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1);
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nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0);
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if (present) {
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NV_INFO(dev, "Load detected on output %c\n", '@' + ffs(dcb->or));
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return connector_status_connected;
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}
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return connector_status_disconnected;
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}
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static bool nv04_dac_mode_fixup(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static void nv04_dac_prepare(struct drm_encoder *encoder)
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{
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struct drm_encoder_helper_funcs *helper = encoder->helper_private;
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int head = nouveau_crtc(encoder->crtc)->index;
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struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
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helper->dpms(encoder, DRM_MODE_DPMS_OFF);
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nv04_dfp_disable(dev, head);
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/* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
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* at LCD__INDEX which we don't alter
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*/
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if (!(crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] & 0x44))
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crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
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}
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static void nv04_dac_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int head = nouveau_crtc(encoder->crtc)->index;
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if (nv_gf4_disp_arch(dev)) {
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struct drm_encoder *rebind;
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uint32_t dac_offset = nv04_dac_output_offset(encoder);
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uint32_t otherdac;
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/* bit 16-19 are bits that are set on some G70 cards,
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* but don't seem to have much effect */
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset,
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head << 8 | NV_PRAMDAC_DACCLK_SEL_DACCLK);
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/* force any other vga encoders to bind to the other crtc */
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list_for_each_entry(rebind, &dev->mode_config.encoder_list, head) {
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if (rebind == encoder
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|| nouveau_encoder(rebind)->dcb->type != OUTPUT_ANALOG)
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continue;
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dac_offset = nv04_dac_output_offset(rebind);
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otherdac = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset);
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset,
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(otherdac & ~0x0100) | (head ^ 1) << 8);
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}
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}
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/* This could use refinement for flatpanels, but it should work this way */
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if (dev_priv->chipset < 0x44)
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
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else
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NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
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}
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static void nv04_dac_commit(struct drm_encoder *encoder)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
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struct drm_encoder_helper_funcs *helper = encoder->helper_private;
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helper->dpms(encoder, DRM_MODE_DPMS_ON);
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NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
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drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
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nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
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}
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void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
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{
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struct drm_device *dev = encoder->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
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if (nv_gf4_disp_arch(dev)) {
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uint32_t *dac_users = &dev_priv->dac_users[ffs(dcb->or) - 1];
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int dacclk_off = NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder);
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uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off);
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if (enable) {
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*dac_users |= 1 << dcb->index;
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NVWriteRAMDAC(dev, 0, dacclk_off, dacclk | NV_PRAMDAC_DACCLK_SEL_DACCLK);
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} else {
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*dac_users &= ~(1 << dcb->index);
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if (!*dac_users)
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NVWriteRAMDAC(dev, 0, dacclk_off,
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dacclk & ~NV_PRAMDAC_DACCLK_SEL_DACCLK);
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}
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}
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}
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static void nv04_dac_dpms(struct drm_encoder *encoder, int mode)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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if (nv_encoder->last_dpms == mode)
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return;
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nv_encoder->last_dpms = mode;
|
|
|
|
NV_INFO(dev, "Setting dpms mode %d on vga encoder (output %d)\n",
|
|
mode, nv_encoder->dcb->index);
|
|
|
|
nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
|
|
}
|
|
|
|
static void nv04_dac_save(struct drm_encoder *encoder)
|
|
{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
nv_encoder->restore.output = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
|
|
nv04_dac_output_offset(encoder));
|
|
}
|
|
|
|
static void nv04_dac_restore(struct drm_encoder *encoder)
|
|
{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder),
|
|
nv_encoder->restore.output);
|
|
|
|
nv_encoder->last_dpms = NV_DPMS_CLEARED;
|
|
}
|
|
|
|
static void nv04_dac_destroy(struct drm_encoder *encoder)
|
|
{
|
|
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
|
|
|
NV_DEBUG_KMS(encoder->dev, "\n");
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(nv_encoder);
|
|
}
|
|
|
|
static const struct drm_encoder_helper_funcs nv04_dac_helper_funcs = {
|
|
.dpms = nv04_dac_dpms,
|
|
.save = nv04_dac_save,
|
|
.restore = nv04_dac_restore,
|
|
.mode_fixup = nv04_dac_mode_fixup,
|
|
.prepare = nv04_dac_prepare,
|
|
.commit = nv04_dac_commit,
|
|
.mode_set = nv04_dac_mode_set,
|
|
.detect = nv04_dac_detect
|
|
};
|
|
|
|
static const struct drm_encoder_helper_funcs nv17_dac_helper_funcs = {
|
|
.dpms = nv04_dac_dpms,
|
|
.save = nv04_dac_save,
|
|
.restore = nv04_dac_restore,
|
|
.mode_fixup = nv04_dac_mode_fixup,
|
|
.prepare = nv04_dac_prepare,
|
|
.commit = nv04_dac_commit,
|
|
.mode_set = nv04_dac_mode_set,
|
|
.detect = nv17_dac_detect
|
|
};
|
|
|
|
static const struct drm_encoder_funcs nv04_dac_funcs = {
|
|
.destroy = nv04_dac_destroy,
|
|
};
|
|
|
|
int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry)
|
|
{
|
|
const struct drm_encoder_helper_funcs *helper;
|
|
struct drm_encoder *encoder;
|
|
struct nouveau_encoder *nv_encoder = NULL;
|
|
|
|
nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
|
|
if (!nv_encoder)
|
|
return -ENOMEM;
|
|
|
|
encoder = to_drm_encoder(nv_encoder);
|
|
|
|
nv_encoder->dcb = entry;
|
|
nv_encoder->or = ffs(entry->or) - 1;
|
|
|
|
if (nv_gf4_disp_arch(dev))
|
|
helper = &nv17_dac_helper_funcs;
|
|
else
|
|
helper = &nv04_dac_helper_funcs;
|
|
|
|
drm_encoder_init(dev, encoder, &nv04_dac_funcs, DRM_MODE_ENCODER_DAC);
|
|
drm_encoder_helper_add(encoder, helper);
|
|
|
|
encoder->possible_crtcs = entry->heads;
|
|
encoder->possible_clones = 0;
|
|
|
|
return 0;
|
|
}
|