716 lines
19 KiB
C
716 lines
19 KiB
C
/*
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* Freescale MPC85xx Memory Controller kernel module
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*
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* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ctype.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/edac.h>
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#include <linux/smp.h>
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#include <linux/gfp.h>
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#include <linux/fsl/edac.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "edac_module.h"
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#include "mpc85xx_edac.h"
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#include "fsl_ddr_edac.h"
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static int edac_dev_idx;
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#ifdef CONFIG_PCI
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static int edac_pci_idx;
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#endif
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/*
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* PCI Err defines
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*/
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#ifdef CONFIG_PCI
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static u32 orig_pci_err_cap_dr;
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static u32 orig_pci_err_en;
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#endif
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static u32 orig_l2_err_disable;
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/**************************** PCI Err device ***************************/
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#ifdef CONFIG_PCI
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static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
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{
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
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/* master aborts can happen during PCI config cycles */
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if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
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return;
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}
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pr_err("PCI error(s) detected\n");
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pr_err("PCI/X ERR_DR register: %#08x\n", err_detect);
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pr_err("PCI/X ERR_ATTRIB register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
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pr_err("PCI/X ERR_ADDR register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
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pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
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pr_err("PCI/X ERR_DL register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
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pr_err("PCI/X ERR_DH register: %#08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
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if (err_detect & PCI_EDE_PERR_MASK)
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edac_pci_handle_pe(pci, pci->ctl_name);
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if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
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edac_pci_handle_npe(pci, pci->ctl_name);
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}
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static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
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{
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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u32 err_detect, err_cap_stat;
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err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
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err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR);
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pr_err("PCIe error(s) detected\n");
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pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
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pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat);
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pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
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pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
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pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
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pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
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in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
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/* reset error capture */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1);
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}
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static int mpc85xx_pcie_find_capability(struct device_node *np)
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{
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struct pci_controller *hose;
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if (!np)
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return -EINVAL;
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hose = pci_find_hose_for_OF_device(np);
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return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
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}
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static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
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{
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struct edac_pci_ctl_info *pci = dev_id;
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
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if (!err_detect)
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return IRQ_NONE;
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if (pdata->is_pcie)
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mpc85xx_pcie_check(pci);
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else
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mpc85xx_pci_check(pci);
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return IRQ_HANDLED;
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}
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static int mpc85xx_pci_err_probe(struct platform_device *op)
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{
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struct edac_pci_ctl_info *pci;
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struct mpc85xx_pci_pdata *pdata;
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struct mpc85xx_edac_pci_plat_data *plat_data;
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struct device_node *of_node;
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struct resource r;
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int res = 0;
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if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
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return -ENOMEM;
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pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
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if (!pci)
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return -ENOMEM;
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/* make sure error reporting method is sane */
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switch (edac_op_state) {
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case EDAC_OPSTATE_POLL:
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case EDAC_OPSTATE_INT:
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break;
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default:
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edac_op_state = EDAC_OPSTATE_INT;
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break;
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}
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pdata = pci->pvt_info;
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pdata->name = "mpc85xx_pci_err";
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plat_data = op->dev.platform_data;
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if (!plat_data) {
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dev_err(&op->dev, "no platform data");
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res = -ENXIO;
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goto err;
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}
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of_node = plat_data->of_node;
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if (mpc85xx_pcie_find_capability(of_node) > 0)
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pdata->is_pcie = true;
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dev_set_drvdata(&op->dev, pci);
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pci->dev = &op->dev;
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pci->mod_name = EDAC_MOD_STR;
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pci->ctl_name = pdata->name;
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pci->dev_name = dev_name(&op->dev);
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if (edac_op_state == EDAC_OPSTATE_POLL) {
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if (pdata->is_pcie)
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pci->edac_check = mpc85xx_pcie_check;
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else
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pci->edac_check = mpc85xx_pci_check;
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}
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pdata->edac_idx = edac_pci_idx++;
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res = of_address_to_resource(of_node, 0, &r);
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if (res) {
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pr_err("%s: Unable to get resource for PCI err regs\n", __func__);
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goto err;
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}
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/* we only need the error registers */
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r.start += 0xe00;
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if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
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pdata->name)) {
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pr_err("%s: Error while requesting mem region\n", __func__);
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res = -EBUSY;
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goto err;
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}
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pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
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if (!pdata->pci_vbase) {
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pr_err("%s: Unable to setup PCI err regs\n", __func__);
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res = -ENOMEM;
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goto err;
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}
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if (pdata->is_pcie) {
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orig_pci_err_cap_dr =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
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orig_pci_err_en =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
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} else {
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orig_pci_err_cap_dr =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
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/* PCI master abort is expected during config cycles */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
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orig_pci_err_en =
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in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
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/* disable master abort reporting */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
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}
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/* clear error bits */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
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/* reset error capture */
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out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1);
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if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
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edac_dbg(3, "failed edac_pci_add_device()\n");
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goto err;
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}
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if (edac_op_state == EDAC_OPSTATE_INT) {
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pdata->irq = irq_of_parse_and_map(of_node, 0);
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res = devm_request_irq(&op->dev, pdata->irq,
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mpc85xx_pci_isr,
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IRQF_SHARED,
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"[EDAC] PCI err", pci);
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if (res < 0) {
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pr_err("%s: Unable to request irq %d for MPC85xx PCI err\n",
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__func__, pdata->irq);
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irq_dispose_mapping(pdata->irq);
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res = -ENODEV;
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goto err2;
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}
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pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n",
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pdata->irq);
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}
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if (pdata->is_pcie) {
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/*
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* Enable all PCIe error interrupt & error detect except invalid
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* PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
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* enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
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* detection enable bit. Because PCIe bus code to initialize and
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* configure these PCIe devices on booting will use some invalid
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* PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
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* notice information. So disable this detect to fix ugly print.
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*/
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
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& ~PEX_ERR_ICCAIE_EN_BIT);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
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| PEX_ERR_ICCAD_DISR_BIT);
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}
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devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
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edac_dbg(3, "success\n");
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pr_info(EDAC_MOD_STR " PCI err registered\n");
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return 0;
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err2:
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edac_pci_del_device(&op->dev);
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err:
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edac_pci_free_ctl_info(pci);
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devres_release_group(&op->dev, mpc85xx_pci_err_probe);
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return res;
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}
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static int mpc85xx_pci_err_remove(struct platform_device *op)
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{
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struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
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edac_dbg(0, "\n");
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, orig_pci_err_cap_dr);
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out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
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edac_pci_del_device(&op->dev);
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edac_pci_free_ctl_info(pci);
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return 0;
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}
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static const struct platform_device_id mpc85xx_pci_err_match[] = {
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{
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.name = "mpc85xx-pci-edac"
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},
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{}
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};
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static struct platform_driver mpc85xx_pci_err_driver = {
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.probe = mpc85xx_pci_err_probe,
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.remove = mpc85xx_pci_err_remove,
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.id_table = mpc85xx_pci_err_match,
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.driver = {
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.name = "mpc85xx_pci_err",
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.suppress_bind_attrs = true,
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},
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};
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#endif /* CONFIG_PCI */
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/**************************** L2 Err device ***************************/
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/************************ L2 SYSFS parts ***********************************/
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static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
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*edac_dev, char *data)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
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}
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static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
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*edac_dev, char *data)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
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}
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static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
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*edac_dev, char *data)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
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}
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static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
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*edac_dev, const char *data,
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size_t count)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
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*edac_dev, const char *data,
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size_t count)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
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*edac_dev, const char *data,
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size_t count)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
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{
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.attr = {
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.name = "inject_data_hi",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_l2_inject_data_hi_show,
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.store = mpc85xx_l2_inject_data_hi_store},
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{
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.attr = {
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.name = "inject_data_lo",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_l2_inject_data_lo_show,
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.store = mpc85xx_l2_inject_data_lo_store},
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{
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.attr = {
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.name = "inject_ctrl",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = mpc85xx_l2_inject_ctrl_show,
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.store = mpc85xx_l2_inject_ctrl_store},
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/* End of list */
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{
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.attr = {.name = NULL}
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}
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};
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static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
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*edac_dev)
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{
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edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
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}
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/***************************** L2 ops ***********************************/
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static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
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{
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struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
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if (!(err_detect & L2_EDE_MASK))
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return;
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pr_err("ECC Error in CPU L2 cache\n");
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pr_err("L2 Error Detect Register: 0x%08x\n", err_detect);
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pr_err("L2 Error Capture Data High Register: 0x%08x\n",
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in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
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pr_err("L2 Error Capture Data Lo Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
|
|
pr_err("L2 Error Syndrome Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
|
|
pr_err("L2 Error Attributes Capture Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
|
|
pr_err("L2 Error Address Capture Register: 0x%08x\n",
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
|
|
|
|
/* clear error detect register */
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
|
|
|
|
if (err_detect & L2_EDE_CE_MASK)
|
|
edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
|
|
|
|
if (err_detect & L2_EDE_UE_MASK)
|
|
edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
|
|
}
|
|
|
|
static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
|
|
{
|
|
struct edac_device_ctl_info *edac_dev = dev_id;
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
u32 err_detect;
|
|
|
|
err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
|
|
|
|
if (!(err_detect & L2_EDE_MASK))
|
|
return IRQ_NONE;
|
|
|
|
mpc85xx_l2_check(edac_dev);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int mpc85xx_l2_err_probe(struct platform_device *op)
|
|
{
|
|
struct edac_device_ctl_info *edac_dev;
|
|
struct mpc85xx_l2_pdata *pdata;
|
|
struct resource r;
|
|
int res;
|
|
|
|
if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
|
|
"cpu", 1, "L", 1, 2, NULL, 0,
|
|
edac_dev_idx);
|
|
if (!edac_dev) {
|
|
devres_release_group(&op->dev, mpc85xx_l2_err_probe);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pdata = edac_dev->pvt_info;
|
|
pdata->name = "mpc85xx_l2_err";
|
|
edac_dev->dev = &op->dev;
|
|
dev_set_drvdata(edac_dev->dev, edac_dev);
|
|
edac_dev->ctl_name = pdata->name;
|
|
edac_dev->dev_name = pdata->name;
|
|
|
|
res = of_address_to_resource(op->dev.of_node, 0, &r);
|
|
if (res) {
|
|
pr_err("%s: Unable to get resource for L2 err regs\n", __func__);
|
|
goto err;
|
|
}
|
|
|
|
/* we only need the error registers */
|
|
r.start += 0xe00;
|
|
|
|
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
|
|
pdata->name)) {
|
|
pr_err("%s: Error while requesting mem region\n", __func__);
|
|
res = -EBUSY;
|
|
goto err;
|
|
}
|
|
|
|
pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
|
|
if (!pdata->l2_vbase) {
|
|
pr_err("%s: Unable to setup L2 err regs\n", __func__);
|
|
res = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
|
|
|
|
orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
|
|
|
|
/* clear the err_dis */
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
|
|
|
|
edac_dev->mod_name = EDAC_MOD_STR;
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL)
|
|
edac_dev->edac_check = mpc85xx_l2_check;
|
|
|
|
mpc85xx_set_l2_sysfs_attributes(edac_dev);
|
|
|
|
pdata->edac_idx = edac_dev_idx++;
|
|
|
|
if (edac_device_add_device(edac_dev) > 0) {
|
|
edac_dbg(3, "failed edac_device_add_device()\n");
|
|
goto err;
|
|
}
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
|
|
res = devm_request_irq(&op->dev, pdata->irq,
|
|
mpc85xx_l2_isr, IRQF_SHARED,
|
|
"[EDAC] L2 err", edac_dev);
|
|
if (res < 0) {
|
|
pr_err("%s: Unable to request irq %d for MPC85xx L2 err\n",
|
|
__func__, pdata->irq);
|
|
irq_dispose_mapping(pdata->irq);
|
|
res = -ENODEV;
|
|
goto err2;
|
|
}
|
|
|
|
pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n", pdata->irq);
|
|
|
|
edac_dev->op_state = OP_RUNNING_INTERRUPT;
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
|
|
}
|
|
|
|
devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
|
|
|
|
edac_dbg(3, "success\n");
|
|
pr_info(EDAC_MOD_STR " L2 err registered\n");
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
edac_device_del_device(&op->dev);
|
|
err:
|
|
devres_release_group(&op->dev, mpc85xx_l2_err_probe);
|
|
edac_device_free_ctl_info(edac_dev);
|
|
return res;
|
|
}
|
|
|
|
static int mpc85xx_l2_err_remove(struct platform_device *op)
|
|
{
|
|
struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
edac_dbg(0, "\n");
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
|
|
irq_dispose_mapping(pdata->irq);
|
|
}
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
|
|
edac_device_del_device(&op->dev);
|
|
edac_device_free_ctl_info(edac_dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mpc85xx_l2_err_of_match[] = {
|
|
{ .compatible = "fsl,mpc8536-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8540-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8541-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8544-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8548-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8555-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8560-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8568-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8569-l2-cache-controller", },
|
|
{ .compatible = "fsl,mpc8572-l2-cache-controller", },
|
|
{ .compatible = "fsl,p1020-l2-cache-controller", },
|
|
{ .compatible = "fsl,p1021-l2-cache-controller", },
|
|
{ .compatible = "fsl,p2020-l2-cache-controller", },
|
|
{ .compatible = "fsl,t2080-l2-cache-controller", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
|
|
|
|
static struct platform_driver mpc85xx_l2_err_driver = {
|
|
.probe = mpc85xx_l2_err_probe,
|
|
.remove = mpc85xx_l2_err_remove,
|
|
.driver = {
|
|
.name = "mpc85xx_l2_err",
|
|
.of_match_table = mpc85xx_l2_err_of_match,
|
|
},
|
|
};
|
|
|
|
static const struct of_device_id mpc85xx_mc_err_of_match[] = {
|
|
{ .compatible = "fsl,mpc8536-memory-controller", },
|
|
{ .compatible = "fsl,mpc8540-memory-controller", },
|
|
{ .compatible = "fsl,mpc8541-memory-controller", },
|
|
{ .compatible = "fsl,mpc8544-memory-controller", },
|
|
{ .compatible = "fsl,mpc8548-memory-controller", },
|
|
{ .compatible = "fsl,mpc8555-memory-controller", },
|
|
{ .compatible = "fsl,mpc8560-memory-controller", },
|
|
{ .compatible = "fsl,mpc8568-memory-controller", },
|
|
{ .compatible = "fsl,mpc8569-memory-controller", },
|
|
{ .compatible = "fsl,mpc8572-memory-controller", },
|
|
{ .compatible = "fsl,mpc8349-memory-controller", },
|
|
{ .compatible = "fsl,p1020-memory-controller", },
|
|
{ .compatible = "fsl,p1021-memory-controller", },
|
|
{ .compatible = "fsl,p2020-memory-controller", },
|
|
{ .compatible = "fsl,qoriq-memory-controller", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
|
|
|
|
static struct platform_driver mpc85xx_mc_err_driver = {
|
|
.probe = fsl_mc_err_probe,
|
|
.remove = fsl_mc_err_remove,
|
|
.driver = {
|
|
.name = "mpc85xx_mc_err",
|
|
.of_match_table = mpc85xx_mc_err_of_match,
|
|
},
|
|
};
|
|
|
|
static struct platform_driver * const drivers[] = {
|
|
&mpc85xx_mc_err_driver,
|
|
&mpc85xx_l2_err_driver,
|
|
#ifdef CONFIG_PCI
|
|
&mpc85xx_pci_err_driver,
|
|
#endif
|
|
};
|
|
|
|
static int __init mpc85xx_mc_init(void)
|
|
{
|
|
int res = 0;
|
|
u32 __maybe_unused pvr = 0;
|
|
|
|
pr_info("Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software\n");
|
|
|
|
/* make sure error reporting method is sane */
|
|
switch (edac_op_state) {
|
|
case EDAC_OPSTATE_POLL:
|
|
case EDAC_OPSTATE_INT:
|
|
break;
|
|
default:
|
|
edac_op_state = EDAC_OPSTATE_INT;
|
|
break;
|
|
}
|
|
|
|
res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
|
if (res)
|
|
pr_warn(EDAC_MOD_STR "drivers fail to register\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
module_init(mpc85xx_mc_init);
|
|
|
|
static void __exit mpc85xx_mc_exit(void)
|
|
{
|
|
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
|
}
|
|
|
|
module_exit(mpc85xx_mc_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Montavista Software, Inc.");
|
|
module_param(edac_op_state, int, 0444);
|
|
MODULE_PARM_DESC(edac_op_state,
|
|
"EDAC Error Reporting state: 0=Poll, 2=Interrupt");
|