349 lines
10 KiB
C
349 lines
10 KiB
C
/*******************************************************************************
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*
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* Intel Ethernet Controller XL710 Family Linux Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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******************************************************************************/
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#include "i40e_prototype.h"
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/**
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* i40e_init_nvm_ops - Initialize NVM function pointers
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* @hw: pointer to the HW structure
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*
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* Setup the function pointers and the NVM info structure. Should be called
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* once per NVM initialization, e.g. inside the i40e_init_shared_code().
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* Please notice that the NVM term is used here (& in all methods covered
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* in this file) as an equivalent of the FLASH part mapped into the SR.
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* We are accessing FLASH always thru the Shadow RAM.
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**/
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i40e_status i40e_init_nvm(struct i40e_hw *hw)
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{
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struct i40e_nvm_info *nvm = &hw->nvm;
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i40e_status ret_code = 0;
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u32 fla, gens;
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u8 sr_size;
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/* The SR size is stored regardless of the nvm programming mode
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* as the blank mode may be used in the factory line.
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*/
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gens = rd32(hw, I40E_GLNVM_GENS);
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sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
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I40E_GLNVM_GENS_SR_SIZE_SHIFT);
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/* Switching to words (sr_size contains power of 2KB) */
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nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
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/* Check if we are in the normal or blank NVM programming mode */
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fla = rd32(hw, I40E_GLNVM_FLA);
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if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
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/* Max NVM timeout */
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nvm->timeout = I40E_MAX_NVM_TIMEOUT;
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nvm->blank_nvm_mode = false;
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} else { /* Blank programming mode */
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nvm->blank_nvm_mode = true;
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ret_code = I40E_ERR_NVM_BLANK_MODE;
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hw_dbg(hw, "NVM init error: unsupported blank mode.\n");
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}
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return ret_code;
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}
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/**
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* i40e_acquire_nvm - Generic request for acquiring the NVM ownership
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* @hw: pointer to the HW structure
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* @access: NVM access type (read or write)
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*
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* This function will request NVM ownership for reading
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* via the proper Admin Command.
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**/
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i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
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enum i40e_aq_resource_access_type access)
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{
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i40e_status ret_code = 0;
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u64 gtime, timeout;
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u64 time = 0;
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if (hw->nvm.blank_nvm_mode)
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goto i40e_i40e_acquire_nvm_exit;
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ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
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0, &time, NULL);
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/* Reading the Global Device Timer */
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gtime = rd32(hw, I40E_GLVFGEN_TIMER);
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/* Store the timeout */
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hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time) + gtime;
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if (ret_code) {
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/* Set the polling timeout */
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if (time > I40E_MAX_NVM_TIMEOUT)
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timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT)
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+ gtime;
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else
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timeout = hw->nvm.hw_semaphore_timeout;
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/* Poll until the current NVM owner timeouts */
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while (gtime < timeout) {
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usleep_range(10000, 20000);
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ret_code = i40e_aq_request_resource(hw,
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I40E_NVM_RESOURCE_ID,
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access, 0, &time,
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NULL);
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if (!ret_code) {
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hw->nvm.hw_semaphore_timeout =
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I40E_MS_TO_GTIME(time) + gtime;
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break;
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}
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gtime = rd32(hw, I40E_GLVFGEN_TIMER);
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}
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if (ret_code) {
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hw->nvm.hw_semaphore_timeout = 0;
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hw->nvm.hw_semaphore_wait =
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I40E_MS_TO_GTIME(time) + gtime;
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hw_dbg(hw, "NVM acquire timed out, wait %llu ms before trying again.\n",
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time);
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}
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}
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i40e_i40e_acquire_nvm_exit:
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return ret_code;
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}
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/**
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* i40e_release_nvm - Generic request for releasing the NVM ownership
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* @hw: pointer to the HW structure
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*
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* This function will release NVM resource via the proper Admin Command.
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**/
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void i40e_release_nvm(struct i40e_hw *hw)
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{
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if (!hw->nvm.blank_nvm_mode)
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i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
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}
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/**
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* i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
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* @hw: pointer to the HW structure
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*
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* Polls the SRCTL Shadow RAM register done bit.
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**/
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static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
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{
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i40e_status ret_code = I40E_ERR_TIMEOUT;
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u32 srctl, wait_cnt;
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/* Poll the I40E_GLNVM_SRCTL until the done bit is set */
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for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
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srctl = rd32(hw, I40E_GLNVM_SRCTL);
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if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
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ret_code = 0;
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break;
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}
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udelay(5);
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}
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if (ret_code == I40E_ERR_TIMEOUT)
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hw_dbg(hw, "Done bit in GLNVM_SRCTL not set\n");
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return ret_code;
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}
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/**
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* i40e_read_nvm_word - Reads Shadow RAM
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
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* @data: word read from the Shadow RAM
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*
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* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
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**/
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i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
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u16 *data)
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{
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i40e_status ret_code = I40E_ERR_TIMEOUT;
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u32 sr_reg;
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if (offset >= hw->nvm.sr_size) {
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hw_dbg(hw, "NVM read error: Offset beyond Shadow RAM limit.\n");
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ret_code = I40E_ERR_PARAM;
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goto read_nvm_exit;
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}
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/* Poll the done bit first */
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ret_code = i40e_poll_sr_srctl_done_bit(hw);
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if (!ret_code) {
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/* Write the address and start reading */
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sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
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(1 << I40E_GLNVM_SRCTL_START_SHIFT);
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wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
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/* Poll I40E_GLNVM_SRCTL until the done bit is set */
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ret_code = i40e_poll_sr_srctl_done_bit(hw);
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if (!ret_code) {
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sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
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*data = (u16)((sr_reg &
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I40E_GLNVM_SRDATA_RDDATA_MASK)
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>> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
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}
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}
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if (ret_code)
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hw_dbg(hw, "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
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offset);
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read_nvm_exit:
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return ret_code;
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}
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/**
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* i40e_read_nvm_buffer - Reads Shadow RAM buffer
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
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* @words: (in) number of words to read; (out) number of words actually read
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* @data: words read from the Shadow RAM
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*
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* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
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* method. The buffer read is preceded by the NVM ownership take
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* and followed by the release.
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**/
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i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
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u16 *words, u16 *data)
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{
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i40e_status ret_code = 0;
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u16 index, word;
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/* Loop thru the selected region */
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for (word = 0; word < *words; word++) {
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index = offset + word;
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ret_code = i40e_read_nvm_word(hw, index, &data[word]);
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if (ret_code)
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break;
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}
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/* Update the number of words read from the Shadow RAM */
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*words = word;
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return ret_code;
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}
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/**
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* i40e_calc_nvm_checksum - Calculates and returns the checksum
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* @hw: pointer to hardware structure
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* @checksum: pointer to the checksum
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*
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* This function calculates SW Checksum that covers the whole 64kB shadow RAM
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* except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
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* is customer specific and unknown. Therefore, this function skips all maximum
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* possible size of VPD (1kB).
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**/
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static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
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u16 *checksum)
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{
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i40e_status ret_code = 0;
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u16 pcie_alt_module = 0;
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u16 checksum_local = 0;
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u16 vpd_module = 0;
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u16 word = 0;
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u32 i = 0;
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/* read pointer to VPD area */
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ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
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if (ret_code) {
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ret_code = I40E_ERR_NVM_CHECKSUM;
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goto i40e_calc_nvm_checksum_exit;
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}
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/* read pointer to PCIe Alt Auto-load module */
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ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
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&pcie_alt_module);
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if (ret_code) {
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ret_code = I40E_ERR_NVM_CHECKSUM;
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goto i40e_calc_nvm_checksum_exit;
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}
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/* Calculate SW checksum that covers the whole 64kB shadow RAM
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* except the VPD and PCIe ALT Auto-load modules
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*/
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for (i = 0; i < hw->nvm.sr_size; i++) {
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/* Skip Checksum word */
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if (i == I40E_SR_SW_CHECKSUM_WORD)
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i++;
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/* Skip VPD module (convert byte size to word count) */
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if (i == (u32)vpd_module) {
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i += (I40E_SR_VPD_MODULE_MAX_SIZE / 2);
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if (i >= hw->nvm.sr_size)
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break;
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}
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/* Skip PCIe ALT module (convert byte size to word count) */
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if (i == (u32)pcie_alt_module) {
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i += (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2);
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if (i >= hw->nvm.sr_size)
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break;
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}
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ret_code = i40e_read_nvm_word(hw, (u16)i, &word);
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if (ret_code) {
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ret_code = I40E_ERR_NVM_CHECKSUM;
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goto i40e_calc_nvm_checksum_exit;
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}
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checksum_local += word;
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}
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*checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
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i40e_calc_nvm_checksum_exit:
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return ret_code;
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}
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/**
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* i40e_validate_nvm_checksum - Validate EEPROM checksum
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* @hw: pointer to hardware structure
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* @checksum: calculated checksum
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*
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* Performs checksum calculation and validates the NVM SW checksum. If the
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* caller does not need checksum, the value can be NULL.
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**/
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i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
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u16 *checksum)
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{
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i40e_status ret_code = 0;
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u16 checksum_sr = 0;
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u16 checksum_local = 0;
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ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
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if (ret_code)
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goto i40e_validate_nvm_checksum_exit;
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/* Do not use i40e_read_nvm_word() because we do not want to take
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* the synchronization semaphores twice here.
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*/
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i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
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/* Verify read checksum from EEPROM is the same as
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* calculated checksum
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*/
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if (checksum_local != checksum_sr)
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ret_code = I40E_ERR_NVM_CHECKSUM;
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/* If the user cares, return the calculated checksum */
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if (checksum)
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*checksum = checksum_local;
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i40e_validate_nvm_checksum_exit:
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return ret_code;
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}
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