521 lines
16 KiB
C
521 lines
16 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#ifndef _CGS_COMMON_H
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#define _CGS_COMMON_H
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#include "amd_shared.h"
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struct cgs_device;
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/**
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* enum cgs_gpu_mem_type - GPU memory types
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*/
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enum cgs_gpu_mem_type {
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CGS_GPU_MEM_TYPE__VISIBLE_FB,
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CGS_GPU_MEM_TYPE__INVISIBLE_FB,
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CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
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CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
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CGS_GPU_MEM_TYPE__GART_CACHEABLE,
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CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
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};
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/**
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* enum cgs_ind_reg - Indirect register spaces
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*/
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enum cgs_ind_reg {
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CGS_IND_REG__MMIO,
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CGS_IND_REG__PCIE,
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CGS_IND_REG__SMC,
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CGS_IND_REG__UVD_CTX,
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CGS_IND_REG__DIDT,
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CGS_IND_REG_GC_CAC,
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CGS_IND_REG__AUDIO_ENDPT
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};
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/**
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* enum cgs_engine - Engines that can be statically power-gated
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*/
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enum cgs_engine {
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CGS_ENGINE__UVD,
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CGS_ENGINE__VCE,
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CGS_ENGINE__VP8,
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CGS_ENGINE__ACP_DMA,
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CGS_ENGINE__ACP_DSP0,
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CGS_ENGINE__ACP_DSP1,
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CGS_ENGINE__ISP,
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/* ... */
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};
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/*
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* enum cgs_ucode_id - Firmware types for different IPs
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*/
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enum cgs_ucode_id {
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CGS_UCODE_ID_SMU = 0,
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CGS_UCODE_ID_SMU_SK,
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CGS_UCODE_ID_SDMA0,
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CGS_UCODE_ID_SDMA1,
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CGS_UCODE_ID_CP_CE,
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CGS_UCODE_ID_CP_PFP,
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CGS_UCODE_ID_CP_ME,
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CGS_UCODE_ID_CP_MEC,
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CGS_UCODE_ID_CP_MEC_JT1,
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CGS_UCODE_ID_CP_MEC_JT2,
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CGS_UCODE_ID_GMCON_RENG,
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CGS_UCODE_ID_RLC_G,
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CGS_UCODE_ID_STORAGE,
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CGS_UCODE_ID_MAXIMUM,
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};
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enum cgs_system_info_id {
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CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
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CGS_SYSTEM_INFO_PCIE_GEN_INFO,
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CGS_SYSTEM_INFO_PCIE_MLW,
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CGS_SYSTEM_INFO_PCIE_DEV,
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CGS_SYSTEM_INFO_PCIE_REV,
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CGS_SYSTEM_INFO_CG_FLAGS,
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CGS_SYSTEM_INFO_PG_FLAGS,
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CGS_SYSTEM_INFO_GFX_CU_INFO,
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CGS_SYSTEM_INFO_GFX_SE_INFO,
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CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
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CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
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CGS_SYSTEM_INFO_ID_MAXIMUM,
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};
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struct cgs_system_info {
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uint64_t size;
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enum cgs_system_info_id info_id;
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union {
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void *ptr;
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uint64_t value;
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};
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uint64_t padding[13];
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};
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/*
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* enum cgs_resource_type - GPU resource type
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*/
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enum cgs_resource_type {
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CGS_RESOURCE_TYPE_MMIO = 0,
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CGS_RESOURCE_TYPE_FB,
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CGS_RESOURCE_TYPE_IO,
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CGS_RESOURCE_TYPE_DOORBELL,
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CGS_RESOURCE_TYPE_ROM,
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};
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/**
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* struct cgs_firmware_info - Firmware information
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*/
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struct cgs_firmware_info {
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uint16_t version;
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uint16_t fw_version;
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uint16_t feature_version;
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uint32_t image_size;
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uint64_t mc_addr;
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/* only for smc firmware */
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uint32_t ucode_start_address;
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void *kptr;
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bool is_kicker;
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};
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struct cgs_mode_info {
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uint32_t refresh_rate;
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uint32_t ref_clock;
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uint32_t vblank_time_us;
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};
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struct cgs_display_info {
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uint32_t display_count;
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uint32_t active_display_mask;
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struct cgs_mode_info *mode_info;
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};
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typedef unsigned long cgs_handle_t;
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#define CGS_ACPI_METHOD_ATCS 0x53435441
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#define CGS_ACPI_METHOD_ATIF 0x46495441
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#define CGS_ACPI_METHOD_ATPX 0x58505441
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#define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
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#define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
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#define CGS_ACPI_MAX_BUFFER_SIZE 256
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#define CGS_ACPI_TYPE_ANY 0x00
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#define CGS_ACPI_TYPE_INTEGER 0x01
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#define CGS_ACPI_TYPE_STRING 0x02
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#define CGS_ACPI_TYPE_BUFFER 0x03
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#define CGS_ACPI_TYPE_PACKAGE 0x04
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struct cgs_acpi_method_argument {
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uint32_t type;
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uint32_t data_length;
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union{
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uint32_t value;
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void *pointer;
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};
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};
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struct cgs_acpi_method_info {
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uint32_t size;
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uint32_t field;
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uint32_t input_count;
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uint32_t name;
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struct cgs_acpi_method_argument *pinput_argument;
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uint32_t output_count;
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struct cgs_acpi_method_argument *poutput_argument;
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uint32_t padding[9];
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};
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/**
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* cgs_alloc_gpu_mem() - Allocate GPU memory
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* @cgs_device: opaque device handle
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* @type: memory type
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* @size: size in bytes
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* @align: alignment in bytes
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* @min_offset: minimum offset from start of heap
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* @max_offset: maximum offset from start of heap
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* @handle: memory handle (output)
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*
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* The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
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* memory allocation. This guarantees that the MC address returned by
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* cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
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* FB memory types may be GART mapped depending on memory
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* fragmentation and memory allocator policies.
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*
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* If min/max_offset are non-0, the allocation will be forced to
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* reside between these offsets in its respective memory heap. The
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* base address that the offset relates to, depends on the memory
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* type.
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*
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* - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
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* - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
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* - others: undefined, don't use with max_offset
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *handle);
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/**
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* cgs_free_gpu_mem() - Free GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_gmap_gpu_mem() - GPU-map GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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* @mcaddr: MC address (output)
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*
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* Ensures that a buffer is GPU accessible and returns its MC address.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
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uint64_t *mcaddr);
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/**
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* cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Allows the buffer to be migrated while it's not used by the GPU.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_kmap_gpu_mem() - Kernel-map GPU memory
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*
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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* @map: Kernel virtual address the memory was mapped to (output)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
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void **map);
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/**
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* cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_read_register() - Read an MMIO register
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* @cgs_device: opaque device handle
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* @offset: register offset
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*
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* Return: register value
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*/
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typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
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/**
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* cgs_write_register() - Write an MMIO register
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* @cgs_device: opaque device handle
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* @offset: register offset
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* @value: register value
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*/
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typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
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uint32_t value);
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/**
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* cgs_read_ind_register() - Read an indirect register
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* @cgs_device: opaque device handle
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* @offset: register offset
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*
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* Return: register value
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*/
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typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
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unsigned index);
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/**
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* cgs_write_ind_register() - Write an indirect register
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* @cgs_device: opaque device handle
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* @offset: register offset
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* @value: register value
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*/
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typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
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unsigned index, uint32_t value);
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/**
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* cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
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* @cgs_device: opaque device handle
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* @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
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* @size: size of the region
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* @offset: offset from the start of the region
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* @resource_base: base address (not including offset) returned
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
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enum cgs_resource_type resource_type,
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uint64_t size,
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uint64_t offset,
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uint64_t *resource_base);
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/**
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* cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
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* @cgs_device: opaque device handle
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* @table: data table index
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* @size: size of the table (output, may be NULL)
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* @frev: table format revision (output, may be NULL)
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* @crev: table content revision (output, may be NULL)
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*
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* Return: Pointer to start of the table, or NULL on failure
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*/
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typedef const void *(*cgs_atom_get_data_table_t)(
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struct cgs_device *cgs_device, unsigned table,
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uint16_t *size, uint8_t *frev, uint8_t *crev);
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/**
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* cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
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* @cgs_device: opaque device handle
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* @table: data table index
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* @frev: table format revision (output, may be NULL)
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* @crev: table content revision (output, may be NULL)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
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uint8_t *frev, uint8_t *crev);
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/**
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* cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
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* @cgs_device: opaque device handle
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* @table: command table index
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* @args: arguments
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
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unsigned table, void *args);
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/**
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* cgs_get_firmware_info - Get the firmware information from core driver
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* @cgs_device: opaque device handle
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* @type: the firmware type
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* @info: returend firmware information
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
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enum cgs_ucode_id type,
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struct cgs_firmware_info *info);
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typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
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enum cgs_ucode_id type);
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typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
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enum amd_ip_block_type block_type,
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enum amd_powergating_state state);
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typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
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enum amd_ip_block_type block_type,
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enum amd_clockgating_state state);
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typedef int(*cgs_get_active_displays_info)(
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struct cgs_device *cgs_device,
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struct cgs_display_info *info);
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typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
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typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
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uint32_t acpi_method,
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uint32_t acpi_function,
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void *pinput, void *poutput,
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uint32_t output_count,
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uint32_t input_size,
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uint32_t output_size);
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typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
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struct cgs_system_info *sys_info);
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typedef int (*cgs_is_virtualization_enabled_t)(void *cgs_device);
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typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
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struct cgs_ops {
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/* memory management calls (similar to KFD interface) */
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cgs_alloc_gpu_mem_t alloc_gpu_mem;
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cgs_free_gpu_mem_t free_gpu_mem;
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cgs_gmap_gpu_mem_t gmap_gpu_mem;
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cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
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cgs_kmap_gpu_mem_t kmap_gpu_mem;
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cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
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/* MMIO access */
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cgs_read_register_t read_register;
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cgs_write_register_t write_register;
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cgs_read_ind_register_t read_ind_register;
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cgs_write_ind_register_t write_ind_register;
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/* PCI resources */
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cgs_get_pci_resource_t get_pci_resource;
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/* ATOM BIOS */
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cgs_atom_get_data_table_t atom_get_data_table;
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cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
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cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
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/* Firmware Info */
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cgs_get_firmware_info get_firmware_info;
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cgs_rel_firmware rel_firmware;
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/* cg pg interface*/
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cgs_set_powergating_state set_powergating_state;
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cgs_set_clockgating_state set_clockgating_state;
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/* display manager */
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cgs_get_active_displays_info get_active_displays_info;
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/* notify dpm enabled */
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cgs_notify_dpm_enabled notify_dpm_enabled;
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/* ACPI */
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cgs_call_acpi_method call_acpi_method;
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/* get system info */
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cgs_query_system_info query_system_info;
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cgs_is_virtualization_enabled_t is_virtualization_enabled;
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cgs_enter_safe_mode enter_safe_mode;
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};
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struct cgs_os_ops; /* To be define in OS-specific CGS header */
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struct cgs_device
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{
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const struct cgs_ops *ops;
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const struct cgs_os_ops *os_ops;
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/* to be embedded at the start of driver private structure */
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};
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/* Convenience macros that make CGS indirect function calls look like
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* normal function calls */
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#define CGS_CALL(func,dev,...) \
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(((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
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#define CGS_OS_CALL(func,dev,...) \
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(((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
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#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
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CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
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#define cgs_free_gpu_mem(dev,handle) \
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CGS_CALL(free_gpu_mem,dev,handle)
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#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
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CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
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#define cgs_gunmap_gpu_mem(dev,handle) \
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CGS_CALL(gunmap_gpu_mem,dev,handle)
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#define cgs_kmap_gpu_mem(dev,handle,map) \
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CGS_CALL(kmap_gpu_mem,dev,handle,map)
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#define cgs_kunmap_gpu_mem(dev,handle) \
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CGS_CALL(kunmap_gpu_mem,dev,handle)
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#define cgs_read_register(dev,offset) \
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CGS_CALL(read_register,dev,offset)
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#define cgs_write_register(dev,offset,value) \
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CGS_CALL(write_register,dev,offset,value)
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#define cgs_read_ind_register(dev,space,index) \
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CGS_CALL(read_ind_register,dev,space,index)
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#define cgs_write_ind_register(dev,space,index,value) \
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CGS_CALL(write_ind_register,dev,space,index,value)
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#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
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CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
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#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
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CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
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#define cgs_atom_exec_cmd_table(dev,table,args) \
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CGS_CALL(atom_exec_cmd_table,dev,table,args)
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#define cgs_get_firmware_info(dev, type, info) \
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CGS_CALL(get_firmware_info, dev, type, info)
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#define cgs_rel_firmware(dev, type) \
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CGS_CALL(rel_firmware, dev, type)
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#define cgs_set_powergating_state(dev, block_type, state) \
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CGS_CALL(set_powergating_state, dev, block_type, state)
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#define cgs_set_clockgating_state(dev, block_type, state) \
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CGS_CALL(set_clockgating_state, dev, block_type, state)
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#define cgs_notify_dpm_enabled(dev, enabled) \
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CGS_CALL(notify_dpm_enabled, dev, enabled)
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#define cgs_get_active_displays_info(dev, info) \
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CGS_CALL(get_active_displays_info, dev, info)
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#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
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CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
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#define cgs_query_system_info(dev, sys_info) \
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CGS_CALL(query_system_info, dev, sys_info)
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#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
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resource_base) \
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CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
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resource_base)
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#define cgs_is_virtualization_enabled(cgs_device) \
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CGS_CALL(is_virtualization_enabled, cgs_device)
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#define cgs_enter_safe_mode(cgs_device, en) \
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CGS_CALL(enter_safe_mode, cgs_device, en)
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#endif /* _CGS_COMMON_H */
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