647 lines
16 KiB
C
647 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra124 DFLL FCPU clock source driver
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*
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* Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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*/
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <soc/tegra/fuse.h>
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#include "clk.h"
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#include "clk-dfll.h"
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#include "cvb.h"
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struct dfll_fcpu_data {
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const unsigned long *cpu_max_freq_table;
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unsigned int cpu_max_freq_table_size;
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const struct cvb_table *cpu_cvb_tables;
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unsigned int cpu_cvb_tables_size;
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};
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/* Maximum CPU frequency, indexed by CPU speedo id */
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static const unsigned long tegra124_cpu_max_freq_table[] = {
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[0] = 2014500000UL,
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[1] = 2320500000UL,
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[2] = 2116500000UL,
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[3] = 2524500000UL,
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};
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static const struct cvb_table tegra124_cpu_cvb_tables[] = {
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{
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.speedo_id = -1,
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.process_id = -1,
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.min_millivolts = 900,
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.max_millivolts = 1260,
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.speedo_scale = 100,
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.voltage_scale = 1000,
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.entries = {
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{ 204000000UL, { 1112619, -29295, 402 } },
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{ 306000000UL, { 1150460, -30585, 402 } },
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{ 408000000UL, { 1190122, -31865, 402 } },
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{ 510000000UL, { 1231606, -33155, 402 } },
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{ 612000000UL, { 1274912, -34435, 402 } },
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{ 714000000UL, { 1320040, -35725, 402 } },
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{ 816000000UL, { 1366990, -37005, 402 } },
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{ 918000000UL, { 1415762, -38295, 402 } },
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{ 1020000000UL, { 1466355, -39575, 402 } },
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{ 1122000000UL, { 1518771, -40865, 402 } },
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{ 1224000000UL, { 1573009, -42145, 402 } },
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{ 1326000000UL, { 1629068, -43435, 402 } },
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{ 1428000000UL, { 1686950, -44715, 402 } },
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{ 1530000000UL, { 1746653, -46005, 402 } },
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{ 1632000000UL, { 1808179, -47285, 402 } },
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{ 1734000000UL, { 1871526, -48575, 402 } },
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{ 1836000000UL, { 1936696, -49855, 402 } },
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{ 1938000000UL, { 2003687, -51145, 402 } },
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{ 2014500000UL, { 2054787, -52095, 402 } },
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{ 2116500000UL, { 2124957, -53385, 402 } },
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{ 2218500000UL, { 2196950, -54665, 402 } },
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{ 2320500000UL, { 2270765, -55955, 402 } },
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{ 2422500000UL, { 2346401, -57235, 402 } },
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{ 2524500000UL, { 2437299, -58535, 402 } },
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{ 0UL, { 0, 0, 0 } },
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},
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.cpu_dfll_data = {
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.tune0_low = 0x005020ff,
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.tune0_high = 0x005040ff,
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.tune1 = 0x00000060,
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}
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},
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};
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static const unsigned long tegra210_cpu_max_freq_table[] = {
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[0] = 1912500000UL,
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[1] = 1912500000UL,
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[2] = 2218500000UL,
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[3] = 1785000000UL,
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[4] = 1632000000UL,
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[5] = 1912500000UL,
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[6] = 2014500000UL,
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[7] = 1734000000UL,
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[8] = 1683000000UL,
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[9] = 1555500000UL,
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[10] = 1504500000UL,
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};
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#define CPU_CVB_TABLE \
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.speedo_scale = 100, \
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.voltage_scale = 1000, \
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.entries = { \
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{ 204000000UL, { 1007452, -23865, 370 } }, \
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{ 306000000UL, { 1052709, -24875, 370 } }, \
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{ 408000000UL, { 1099069, -25895, 370 } }, \
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{ 510000000UL, { 1146534, -26905, 370 } }, \
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{ 612000000UL, { 1195102, -27915, 370 } }, \
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{ 714000000UL, { 1244773, -28925, 370 } }, \
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{ 816000000UL, { 1295549, -29935, 370 } }, \
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{ 918000000UL, { 1347428, -30955, 370 } }, \
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{ 1020000000UL, { 1400411, -31965, 370 } }, \
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{ 1122000000UL, { 1454497, -32975, 370 } }, \
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{ 1224000000UL, { 1509687, -33985, 370 } }, \
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{ 1326000000UL, { 1565981, -35005, 370 } }, \
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{ 1428000000UL, { 1623379, -36015, 370 } }, \
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{ 1530000000UL, { 1681880, -37025, 370 } }, \
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{ 1632000000UL, { 1741485, -38035, 370 } }, \
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{ 1734000000UL, { 1802194, -39055, 370 } }, \
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{ 1836000000UL, { 1864006, -40065, 370 } }, \
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{ 1912500000UL, { 1910780, -40815, 370 } }, \
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{ 2014500000UL, { 1227000, 0, 0 } }, \
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{ 2218500000UL, { 1227000, 0, 0 } }, \
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{ 0UL, { 0, 0, 0 } }, \
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}
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#define CPU_CVB_TABLE_XA \
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.speedo_scale = 100, \
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.voltage_scale = 1000, \
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.entries = { \
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{ 204000000UL, { 1250024, -39785, 565 } }, \
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{ 306000000UL, { 1297556, -41145, 565 } }, \
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{ 408000000UL, { 1346718, -42505, 565 } }, \
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{ 510000000UL, { 1397511, -43855, 565 } }, \
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{ 612000000UL, { 1449933, -45215, 565 } }, \
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{ 714000000UL, { 1503986, -46575, 565 } }, \
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{ 816000000UL, { 1559669, -47935, 565 } }, \
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{ 918000000UL, { 1616982, -49295, 565 } }, \
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{ 1020000000UL, { 1675926, -50645, 565 } }, \
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{ 1122000000UL, { 1736500, -52005, 565 } }, \
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{ 1224000000UL, { 1798704, -53365, 565 } }, \
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{ 1326000000UL, { 1862538, -54725, 565 } }, \
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{ 1428000000UL, { 1928003, -56085, 565 } }, \
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{ 1530000000UL, { 1995097, -57435, 565 } }, \
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{ 1606500000UL, { 2046149, -58445, 565 } }, \
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{ 1632000000UL, { 2063822, -58795, 565 } }, \
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{ 0UL, { 0, 0, 0 } }, \
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}
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#define CPU_CVB_TABLE_EUCM1 \
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.speedo_scale = 100, \
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.voltage_scale = 1000, \
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.entries = { \
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{ 204000000UL, { 734429, 0, 0 } }, \
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{ 306000000UL, { 768191, 0, 0 } }, \
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{ 408000000UL, { 801953, 0, 0 } }, \
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{ 510000000UL, { 835715, 0, 0 } }, \
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{ 612000000UL, { 869477, 0, 0 } }, \
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{ 714000000UL, { 903239, 0, 0 } }, \
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{ 816000000UL, { 937001, 0, 0 } }, \
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{ 918000000UL, { 970763, 0, 0 } }, \
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{ 1020000000UL, { 1004525, 0, 0 } }, \
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{ 1122000000UL, { 1038287, 0, 0 } }, \
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{ 1224000000UL, { 1072049, 0, 0 } }, \
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{ 1326000000UL, { 1105811, 0, 0 } }, \
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{ 1428000000UL, { 1130000, 0, 0 } }, \
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{ 1555500000UL, { 1130000, 0, 0 } }, \
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{ 1632000000UL, { 1170000, 0, 0 } }, \
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{ 1734000000UL, { 1227500, 0, 0 } }, \
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{ 0UL, { 0, 0, 0 } }, \
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}
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#define CPU_CVB_TABLE_EUCM2 \
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.speedo_scale = 100, \
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.voltage_scale = 1000, \
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.entries = { \
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{ 204000000UL, { 742283, 0, 0 } }, \
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{ 306000000UL, { 776249, 0, 0 } }, \
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{ 408000000UL, { 810215, 0, 0 } }, \
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{ 510000000UL, { 844181, 0, 0 } }, \
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{ 612000000UL, { 878147, 0, 0 } }, \
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{ 714000000UL, { 912113, 0, 0 } }, \
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{ 816000000UL, { 946079, 0, 0 } }, \
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{ 918000000UL, { 980045, 0, 0 } }, \
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{ 1020000000UL, { 1014011, 0, 0 } }, \
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{ 1122000000UL, { 1047977, 0, 0 } }, \
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{ 1224000000UL, { 1081943, 0, 0 } }, \
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{ 1326000000UL, { 1090000, 0, 0 } }, \
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{ 1479000000UL, { 1090000, 0, 0 } }, \
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{ 1555500000UL, { 1162000, 0, 0 } }, \
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{ 1683000000UL, { 1195000, 0, 0 } }, \
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{ 0UL, { 0, 0, 0 } }, \
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}
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#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
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.speedo_scale = 100, \
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.voltage_scale = 1000, \
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.entries = { \
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{ 204000000UL, { 742283, 0, 0 } }, \
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{ 306000000UL, { 776249, 0, 0 } }, \
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{ 408000000UL, { 810215, 0, 0 } }, \
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{ 510000000UL, { 844181, 0, 0 } }, \
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{ 612000000UL, { 878147, 0, 0 } }, \
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{ 714000000UL, { 912113, 0, 0 } }, \
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{ 816000000UL, { 946079, 0, 0 } }, \
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{ 918000000UL, { 980045, 0, 0 } }, \
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{ 1020000000UL, { 1014011, 0, 0 } }, \
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{ 1122000000UL, { 1047977, 0, 0 } }, \
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{ 1224000000UL, { 1081943, 0, 0 } }, \
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{ 1326000000UL, { 1090000, 0, 0 } }, \
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{ 1479000000UL, { 1090000, 0, 0 } }, \
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{ 1504500000UL, { 1120000, 0, 0 } }, \
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{ 0UL, { 0, 0, 0 } }, \
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}
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#define CPU_CVB_TABLE_ODN \
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.speedo_scale = 100, \
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.voltage_scale = 1000, \
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.entries = { \
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{ 204000000UL, { 721094, 0, 0 } }, \
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{ 306000000UL, { 754040, 0, 0 } }, \
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{ 408000000UL, { 786986, 0, 0 } }, \
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{ 510000000UL, { 819932, 0, 0 } }, \
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{ 612000000UL, { 852878, 0, 0 } }, \
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{ 714000000UL, { 885824, 0, 0 } }, \
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{ 816000000UL, { 918770, 0, 0 } }, \
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{ 918000000UL, { 915716, 0, 0 } }, \
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{ 1020000000UL, { 984662, 0, 0 } }, \
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{ 1122000000UL, { 1017608, 0, 0 } }, \
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{ 1224000000UL, { 1050554, 0, 0 } }, \
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{ 1326000000UL, { 1083500, 0, 0 } }, \
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{ 1428000000UL, { 1116446, 0, 0 } }, \
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{ 1581000000UL, { 1130000, 0, 0 } }, \
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{ 1683000000UL, { 1168000, 0, 0 } }, \
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{ 1785000000UL, { 1227500, 0, 0 } }, \
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{ 0UL, { 0, 0, 0 } }, \
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}
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static struct cvb_table tegra210_cpu_cvb_tables[] = {
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{
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.speedo_id = 10,
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.process_id = 0,
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.min_millivolts = 840,
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.max_millivolts = 1120,
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CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 10,
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.process_id = 1,
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.min_millivolts = 840,
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.max_millivolts = 1120,
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CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 9,
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.process_id = 0,
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.min_millivolts = 900,
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.max_millivolts = 1162,
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CPU_CVB_TABLE_EUCM2,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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}
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},
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{
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.speedo_id = 9,
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.process_id = 1,
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.min_millivolts = 900,
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.max_millivolts = 1162,
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CPU_CVB_TABLE_EUCM2,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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}
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},
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{
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.speedo_id = 8,
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.process_id = 0,
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.min_millivolts = 900,
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.max_millivolts = 1195,
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CPU_CVB_TABLE_EUCM2,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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}
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},
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{
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.speedo_id = 8,
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.process_id = 1,
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.min_millivolts = 900,
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.max_millivolts = 1195,
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CPU_CVB_TABLE_EUCM2,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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}
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},
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{
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.speedo_id = 7,
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.process_id = 0,
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.min_millivolts = 841,
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.max_millivolts = 1227,
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CPU_CVB_TABLE_EUCM1,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 7,
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.process_id = 1,
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.min_millivolts = 841,
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.max_millivolts = 1227,
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CPU_CVB_TABLE_EUCM1,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 6,
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.process_id = 0,
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.min_millivolts = 870,
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.max_millivolts = 1150,
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CPU_CVB_TABLE,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune1 = 0x20091d9,
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}
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},
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{
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.speedo_id = 6,
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.process_id = 1,
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.min_millivolts = 870,
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.max_millivolts = 1150,
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CPU_CVB_TABLE,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune1 = 0x25501d0,
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}
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},
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{
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.speedo_id = 5,
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.process_id = 0,
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.min_millivolts = 818,
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.max_millivolts = 1227,
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CPU_CVB_TABLE,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 5,
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.process_id = 1,
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.min_millivolts = 818,
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.max_millivolts = 1227,
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CPU_CVB_TABLE,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x25501d0,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 4,
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.process_id = -1,
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.min_millivolts = 918,
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.max_millivolts = 1113,
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CPU_CVB_TABLE_XA,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune1 = 0x17711BD,
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}
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},
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{
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.speedo_id = 3,
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.process_id = 0,
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.min_millivolts = 825,
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.max_millivolts = 1227,
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CPU_CVB_TABLE_ODN,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x20091d9,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 3,
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.process_id = 1,
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.min_millivolts = 825,
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.max_millivolts = 1227,
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CPU_CVB_TABLE_ODN,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune0_high = 0xffead0ff,
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.tune1 = 0x25501d0,
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.tune_high_min_millivolts = 864,
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}
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},
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{
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.speedo_id = 2,
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.process_id = 0,
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.min_millivolts = 870,
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.max_millivolts = 1227,
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CPU_CVB_TABLE,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
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.tune1 = 0x20091d9,
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}
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},
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{
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.speedo_id = 2,
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.process_id = 1,
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.min_millivolts = 870,
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.max_millivolts = 1227,
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CPU_CVB_TABLE,
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.cpu_dfll_data = {
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.tune0_low = 0xffead0ff,
|
|
.tune1 = 0x25501d0,
|
|
}
|
|
},
|
|
{
|
|
.speedo_id = 1,
|
|
.process_id = 0,
|
|
.min_millivolts = 837,
|
|
.max_millivolts = 1227,
|
|
CPU_CVB_TABLE,
|
|
.cpu_dfll_data = {
|
|
.tune0_low = 0xffead0ff,
|
|
.tune0_high = 0xffead0ff,
|
|
.tune1 = 0x20091d9,
|
|
.tune_high_min_millivolts = 864,
|
|
}
|
|
},
|
|
{
|
|
.speedo_id = 1,
|
|
.process_id = 1,
|
|
.min_millivolts = 837,
|
|
.max_millivolts = 1227,
|
|
CPU_CVB_TABLE,
|
|
.cpu_dfll_data = {
|
|
.tune0_low = 0xffead0ff,
|
|
.tune0_high = 0xffead0ff,
|
|
.tune1 = 0x25501d0,
|
|
.tune_high_min_millivolts = 864,
|
|
}
|
|
},
|
|
{
|
|
.speedo_id = 0,
|
|
.process_id = 0,
|
|
.min_millivolts = 850,
|
|
.max_millivolts = 1170,
|
|
CPU_CVB_TABLE,
|
|
.cpu_dfll_data = {
|
|
.tune0_low = 0xffead0ff,
|
|
.tune0_high = 0xffead0ff,
|
|
.tune1 = 0x20091d9,
|
|
.tune_high_min_millivolts = 864,
|
|
}
|
|
},
|
|
{
|
|
.speedo_id = 0,
|
|
.process_id = 1,
|
|
.min_millivolts = 850,
|
|
.max_millivolts = 1170,
|
|
CPU_CVB_TABLE,
|
|
.cpu_dfll_data = {
|
|
.tune0_low = 0xffead0ff,
|
|
.tune0_high = 0xffead0ff,
|
|
.tune1 = 0x25501d0,
|
|
.tune_high_min_millivolts = 864,
|
|
}
|
|
},
|
|
};
|
|
|
|
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
|
|
.cpu_max_freq_table = tegra124_cpu_max_freq_table,
|
|
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
|
|
.cpu_cvb_tables = tegra124_cpu_cvb_tables,
|
|
.cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
|
|
};
|
|
|
|
static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
|
|
.cpu_max_freq_table = tegra210_cpu_max_freq_table,
|
|
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table),
|
|
.cpu_cvb_tables = tegra210_cpu_cvb_tables,
|
|
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
|
|
};
|
|
|
|
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
|
|
{
|
|
.compatible = "nvidia,tegra124-dfll",
|
|
.data = &tegra124_dfll_fcpu_data,
|
|
},
|
|
{
|
|
.compatible = "nvidia,tegra210-dfll",
|
|
.data = &tegra210_dfll_fcpu_data
|
|
},
|
|
{ },
|
|
};
|
|
|
|
static void get_alignment_from_dt(struct device *dev,
|
|
struct rail_alignment *align)
|
|
{
|
|
if (of_property_read_u32(dev->of_node,
|
|
"nvidia,pwm-voltage-step-microvolts",
|
|
&align->step_uv))
|
|
align->step_uv = 0;
|
|
|
|
if (of_property_read_u32(dev->of_node,
|
|
"nvidia,pwm-min-microvolts",
|
|
&align->offset_uv))
|
|
align->offset_uv = 0;
|
|
}
|
|
|
|
static int get_alignment_from_regulator(struct device *dev,
|
|
struct rail_alignment *align)
|
|
{
|
|
struct regulator *reg = regulator_get(dev, "vdd-cpu");
|
|
|
|
if (IS_ERR(reg))
|
|
return PTR_ERR(reg);
|
|
|
|
align->offset_uv = regulator_list_voltage(reg, 0);
|
|
align->step_uv = regulator_get_linear_step(reg);
|
|
|
|
regulator_put(reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
|
|
{
|
|
int process_id, speedo_id, speedo_value, err;
|
|
struct tegra_dfll_soc_data *soc;
|
|
const struct dfll_fcpu_data *fcpu_data;
|
|
struct rail_alignment align;
|
|
|
|
fcpu_data = of_device_get_match_data(&pdev->dev);
|
|
if (!fcpu_data)
|
|
return -ENODEV;
|
|
|
|
process_id = tegra_sku_info.cpu_process_id;
|
|
speedo_id = tegra_sku_info.cpu_speedo_id;
|
|
speedo_value = tegra_sku_info.cpu_speedo_value;
|
|
|
|
if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
|
|
dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
|
|
speedo_id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
|
|
if (!soc)
|
|
return -ENOMEM;
|
|
|
|
soc->dev = get_cpu_device(0);
|
|
if (!soc->dev) {
|
|
dev_err(&pdev->dev, "no CPU0 device\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")) {
|
|
get_alignment_from_dt(&pdev->dev, &align);
|
|
} else {
|
|
err = get_alignment_from_regulator(&pdev->dev, &align);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
|
|
|
|
soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
|
|
fcpu_data->cpu_cvb_tables_size,
|
|
&align, process_id, speedo_id,
|
|
speedo_value, soc->max_freq);
|
|
soc->alignment = align;
|
|
|
|
if (IS_ERR(soc->cvb)) {
|
|
dev_err(&pdev->dev, "couldn't add OPP table: %ld\n",
|
|
PTR_ERR(soc->cvb));
|
|
return PTR_ERR(soc->cvb);
|
|
}
|
|
|
|
err = tegra_dfll_register(pdev, soc);
|
|
if (err < 0) {
|
|
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_dfll_soc_data *soc;
|
|
|
|
soc = tegra_dfll_unregister(pdev);
|
|
if (IS_ERR(soc)) {
|
|
dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n",
|
|
PTR_ERR(soc));
|
|
return PTR_ERR(soc);
|
|
}
|
|
|
|
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra124_dfll_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
|
|
tegra_dfll_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra124_dfll_fcpu_driver = {
|
|
.probe = tegra124_dfll_fcpu_probe,
|
|
.remove = tegra124_dfll_fcpu_remove,
|
|
.driver = {
|
|
.name = "tegra124-dfll",
|
|
.of_match_table = tegra124_dfll_fcpu_of_match,
|
|
.pm = &tegra124_dfll_pm_ops,
|
|
},
|
|
};
|
|
builtin_platform_driver(tegra124_dfll_fcpu_driver);
|