496 lines
13 KiB
C
496 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
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*
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* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*
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* Based on the BSP (called "UGW") driver:
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* Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
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* Copyright (C) 2016 Intel Corporation
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*
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* TODO: PHY modes other than 36MHz (without "SSC")
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
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#define PCIE_PHY_PLL_CTRL1 0x44
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#define PCIE_PHY_PLL_CTRL2 0x46
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#define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK GENMASK(7, 0)
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#define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN BIT(8)
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#define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN BIT(9)
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#define PCIE_PHY_PLL_CTRL3 0x48
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#define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN BIT(1)
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#define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK GENMASK(6, 4)
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#define PCIE_PHY_PLL_CTRL4 0x4a
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#define PCIE_PHY_PLL_CTRL5 0x4c
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#define PCIE_PHY_PLL_CTRL6 0x4e
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#define PCIE_PHY_PLL_CTRL7 0x50
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#define PCIE_PHY_PLL_A_CTRL1 0x52
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#define PCIE_PHY_PLL_A_CTRL2 0x54
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#define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN BIT(14)
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#define PCIE_PHY_PLL_A_CTRL3 0x56
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#define PCIE_PHY_PLL_A_CTRL3_MMD_MASK GENMASK(15, 13)
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#define PCIE_PHY_PLL_STATUS 0x58
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#define PCIE_PHY_TX1_CTRL1 0x60
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#define PCIE_PHY_TX1_CTRL1_FORCE_EN BIT(3)
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#define PCIE_PHY_TX1_CTRL1_LOAD_EN BIT(4)
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#define PCIE_PHY_TX1_CTRL2 0x62
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#define PCIE_PHY_TX1_CTRL3 0x64
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#define PCIE_PHY_TX1_A_CTRL1 0x66
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#define PCIE_PHY_TX1_A_CTRL2 0x68
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#define PCIE_PHY_TX1_MOD1 0x6a
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#define PCIE_PHY_TX1_MOD2 0x6c
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#define PCIE_PHY_TX1_MOD3 0x6e
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#define PCIE_PHY_TX2_CTRL1 0x70
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#define PCIE_PHY_TX2_CTRL1_LOAD_EN BIT(4)
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#define PCIE_PHY_TX2_CTRL2 0x72
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#define PCIE_PHY_TX2_A_CTRL1 0x76
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#define PCIE_PHY_TX2_A_CTRL2 0x78
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#define PCIE_PHY_TX2_MOD1 0x7a
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#define PCIE_PHY_TX2_MOD2 0x7c
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#define PCIE_PHY_TX2_MOD3 0x7e
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#define PCIE_PHY_RX1_CTRL1 0xa0
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#define PCIE_PHY_RX1_CTRL1_LOAD_EN BIT(1)
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#define PCIE_PHY_RX1_CTRL2 0xa2
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#define PCIE_PHY_RX1_CDR 0xa4
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#define PCIE_PHY_RX1_EI 0xa6
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#define PCIE_PHY_RX1_A_CTRL 0xaa
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struct ltq_vrx200_pcie_phy_priv {
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struct phy *phy;
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unsigned int mode;
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struct device *dev;
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struct regmap *phy_regmap;
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struct regmap *rcu_regmap;
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struct clk *pdi_clk;
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struct clk *phy_clk;
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struct reset_control *phy_reset;
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struct reset_control *pcie_reset;
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u32 rcu_ahb_endian_offset;
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u32 rcu_ahb_endian_big_endian_mask;
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};
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static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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/* PLL Setting */
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
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/* increase the bias reference voltage */
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
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/* Endcnt */
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regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
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regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
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PCIE_PHY_TX1_CTRL1_FORCE_EN,
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PCIE_PHY_TX1_CTRL1_FORCE_EN);
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/* predrv_ser_en */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
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/* ctrl_lim */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
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/* ctrl */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
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/* predrv_ser_en */
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
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0x4700);
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/* RTERM */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
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/* Improved 100MHz clock output */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
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/* Reduced CDR BW to avoid glitches */
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regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
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}
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static void pcie_phy_36mhz_mode_setup(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
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PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
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PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
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PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
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PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
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PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
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PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
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PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
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FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
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PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);
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/* const_sdm */
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
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regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
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PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
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FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
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0xee));
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/* pllmod */
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
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regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
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}
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static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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unsigned int tmp;
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int ret;
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ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
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tmp, ((tmp & 0x0070) == 0x0070), 10,
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10000);
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if (ret) {
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dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",
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tmp);
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return ret;
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}
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return 0;
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}
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static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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static const struct reg_default slices[] = {
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{
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.reg = PCIE_PHY_TX1_CTRL1,
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.def = PCIE_PHY_TX1_CTRL1_LOAD_EN,
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},
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{
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.reg = PCIE_PHY_TX2_CTRL1,
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.def = PCIE_PHY_TX2_CTRL1_LOAD_EN,
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},
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{
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.reg = PCIE_PHY_RX1_CTRL1,
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.def = PCIE_PHY_RX1_CTRL1_LOAD_EN,
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}
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(slices); i++) {
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/* enable load_en */
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regmap_update_bits(priv->phy_regmap, slices[i].reg,
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slices[i].def, slices[i].def);
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udelay(1);
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/* disable load_en */
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regmap_update_bits(priv->phy_regmap, slices[i].reg,
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slices[i].def, 0x0);
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}
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for (i = 0; i < 5; i++) {
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/* TX2 modulation */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
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usleep_range(1000, 2000);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
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/* TX1 modulation */
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
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usleep_range(1000, 2000);
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regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
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}
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}
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static int ltq_vrx200_pcie_phy_init(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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int ret;
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if (of_device_is_big_endian(priv->dev->of_node))
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regmap_update_bits(priv->rcu_regmap,
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priv->rcu_ahb_endian_offset,
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priv->rcu_ahb_endian_big_endian_mask,
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priv->rcu_ahb_endian_big_endian_mask);
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else
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regmap_update_bits(priv->rcu_regmap,
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priv->rcu_ahb_endian_offset,
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priv->rcu_ahb_endian_big_endian_mask, 0x0);
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ret = reset_control_assert(priv->phy_reset);
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if (ret)
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goto err;
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udelay(1);
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ret = reset_control_deassert(priv->phy_reset);
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if (ret)
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goto err;
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udelay(1);
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ret = reset_control_deassert(priv->pcie_reset);
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if (ret)
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goto err_assert_phy_reset;
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/* Make sure PHY PLL is stable */
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usleep_range(20, 40);
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return 0;
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err_assert_phy_reset:
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reset_control_assert(priv->phy_reset);
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err:
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return ret;
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}
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static int ltq_vrx200_pcie_phy_exit(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = reset_control_assert(priv->pcie_reset);
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if (ret)
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return ret;
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ret = reset_control_assert(priv->phy_reset);
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if (ret)
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return ret;
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return 0;
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}
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static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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int ret;
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/* Enable PDI to access PCIe PHY register */
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ret = clk_prepare_enable(priv->pdi_clk);
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if (ret)
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goto err;
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/* Configure PLL and PHY clock */
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ltq_vrx200_pcie_phy_common_setup(phy);
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pcie_phy_36mhz_mode_setup(phy);
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/* Enable the PCIe PHY and make PLL setting take effect */
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ret = clk_prepare_enable(priv->phy_clk);
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if (ret)
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goto err_disable_pdi_clk;
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/* Check if we are in "startup ready" status */
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ret = ltq_vrx200_pcie_phy_wait_for_pll(phy);
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if (ret)
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goto err_disable_phy_clk;
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ltq_vrx200_pcie_phy_apply_workarounds(phy);
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return 0;
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err_disable_phy_clk:
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clk_disable_unprepare(priv->phy_clk);
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err_disable_pdi_clk:
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clk_disable_unprepare(priv->pdi_clk);
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err:
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return ret;
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}
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static int ltq_vrx200_pcie_phy_power_off(struct phy *phy)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
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clk_disable_unprepare(priv->phy_clk);
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clk_disable_unprepare(priv->pdi_clk);
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return 0;
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}
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static const struct phy_ops ltq_vrx200_pcie_phy_ops = {
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.init = ltq_vrx200_pcie_phy_init,
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.exit = ltq_vrx200_pcie_phy_exit,
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.power_on = ltq_vrx200_pcie_phy_power_on,
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.power_off = ltq_vrx200_pcie_phy_power_off,
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.owner = THIS_MODULE,
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};
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static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct ltq_vrx200_pcie_phy_priv *priv = dev_get_drvdata(dev);
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unsigned int mode;
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if (args->args_count != 1) {
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dev_err(dev, "invalid number of arguments\n");
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return ERR_PTR(-EINVAL);
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}
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mode = args->args[0];
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switch (mode) {
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case LANTIQ_PCIE_PHY_MODE_36MHZ:
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priv->mode = mode;
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break;
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case LANTIQ_PCIE_PHY_MODE_25MHZ:
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case LANTIQ_PCIE_PHY_MODE_25MHZ_SSC:
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case LANTIQ_PCIE_PHY_MODE_36MHZ_SSC:
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case LANTIQ_PCIE_PHY_MODE_100MHZ:
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case LANTIQ_PCIE_PHY_MODE_100MHZ_SSC:
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dev_err(dev, "PHY mode not implemented yet: %u\n", mode);
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return ERR_PTR(-EINVAL);
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default:
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dev_err(dev, "invalid PHY mode %u\n", mode);
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return ERR_PTR(-EINVAL);
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}
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return priv->phy;
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}
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static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev)
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{
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static const struct regmap_config regmap_config = {
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.reg_bits = 8,
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.val_bits = 16,
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.reg_stride = 2,
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.max_register = PCIE_PHY_RX1_A_CTRL,
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};
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struct ltq_vrx200_pcie_phy_priv *priv;
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struct device *dev = &pdev->dev;
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struct phy_provider *provider;
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struct resource *res;
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void __iomem *base;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->phy_regmap = devm_regmap_init_mmio(dev, base, ®map_config);
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if (IS_ERR(priv->phy_regmap))
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return PTR_ERR(priv->phy_regmap);
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priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"lantiq,rcu");
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if (IS_ERR(priv->rcu_regmap))
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return PTR_ERR(priv->rcu_regmap);
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ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset",
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&priv->rcu_ahb_endian_offset);
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if (ret) {
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dev_err(dev,
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"failed to parse the 'lantiq,rcu-endian-offset' property\n");
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return ret;
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}
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ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask",
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&priv->rcu_ahb_endian_big_endian_mask);
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if (ret) {
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dev_err(dev,
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"failed to parse the 'lantiq,rcu-big-endian-mask' property\n");
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return ret;
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}
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priv->pdi_clk = devm_clk_get(dev, "pdi");
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if (IS_ERR(priv->pdi_clk))
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return PTR_ERR(priv->pdi_clk);
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priv->phy_clk = devm_clk_get(dev, "phy");
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if (IS_ERR(priv->phy_clk))
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return PTR_ERR(priv->phy_clk);
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priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
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if (IS_ERR(priv->phy_reset))
|
|
return PTR_ERR(priv->phy_reset);
|
|
|
|
priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie");
|
|
if (IS_ERR(priv->pcie_reset))
|
|
return PTR_ERR(priv->pcie_reset);
|
|
|
|
priv->dev = dev;
|
|
|
|
priv->phy = devm_phy_create(dev, dev->of_node,
|
|
<q_vrx200_pcie_phy_ops);
|
|
if (IS_ERR(priv->phy)) {
|
|
dev_err(dev, "failed to create PHY\n");
|
|
return PTR_ERR(priv->phy);
|
|
}
|
|
|
|
phy_set_drvdata(priv->phy, priv);
|
|
dev_set_drvdata(dev, priv);
|
|
|
|
provider = devm_of_phy_provider_register(dev,
|
|
ltq_vrx200_pcie_phy_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(provider);
|
|
}
|
|
|
|
static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = {
|
|
{ .compatible = "lantiq,vrx200-pcie-phy", },
|
|
{ .compatible = "lantiq,arx300-pcie-phy", },
|
|
{ /* sentinel */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match);
|
|
|
|
static struct platform_driver ltq_vrx200_pcie_phy_driver = {
|
|
.probe = ltq_vrx200_pcie_phy_probe,
|
|
.driver = {
|
|
.name = "ltq-vrx200-pcie-phy",
|
|
.of_match_table = ltq_vrx200_pcie_phy_of_match,
|
|
}
|
|
};
|
|
module_platform_driver(ltq_vrx200_pcie_phy_driver);
|
|
|
|
MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
|
|
MODULE_DESCRIPTION("Lantiq VRX200 and ARX300 PCIe PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|