733 lines
18 KiB
C
733 lines
18 KiB
C
/*
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* Driver for Amlogic Meson AO CEC Controller
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved
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* Copyright (C) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <media/cec.h>
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#include <media/cec-notifier.h>
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/* CEC Registers */
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/*
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* [2:1] cntl_clk
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* - 0 = Disable clk (Power-off mode)
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* - 1 = Enable gated clock (Normal mode)
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* - 2 = Enable free-run clk (Debug mode)
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*/
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#define CEC_GEN_CNTL_REG 0x00
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#define CEC_GEN_CNTL_RESET BIT(0)
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#define CEC_GEN_CNTL_CLK_DISABLE 0
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#define CEC_GEN_CNTL_CLK_ENABLE 1
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#define CEC_GEN_CNTL_CLK_ENABLE_DBG 2
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#define CEC_GEN_CNTL_CLK_CTRL_MASK GENMASK(2, 1)
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/*
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* [7:0] cec_reg_addr
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* [15:8] cec_reg_wrdata
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* [16] cec_reg_wr
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* - 0 = Read
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* - 1 = Write
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* [23] bus free
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* [31:24] cec_reg_rddata
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*/
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#define CEC_RW_REG 0x04
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#define CEC_RW_ADDR GENMASK(7, 0)
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#define CEC_RW_WR_DATA GENMASK(15, 8)
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#define CEC_RW_WRITE_EN BIT(16)
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#define CEC_RW_BUS_BUSY BIT(23)
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#define CEC_RW_RD_DATA GENMASK(31, 24)
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/*
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* [1] tx intr
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* [2] rx intr
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*/
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#define CEC_INTR_MASKN_REG 0x08
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#define CEC_INTR_CLR_REG 0x0c
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#define CEC_INTR_STAT_REG 0x10
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#define CEC_INTR_TX BIT(1)
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#define CEC_INTR_RX BIT(2)
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/* CEC Commands */
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#define CEC_TX_MSG_0_HEADER 0x00
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#define CEC_TX_MSG_1_OPCODE 0x01
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#define CEC_TX_MSG_2_OP1 0x02
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#define CEC_TX_MSG_3_OP2 0x03
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#define CEC_TX_MSG_4_OP3 0x04
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#define CEC_TX_MSG_5_OP4 0x05
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#define CEC_TX_MSG_6_OP5 0x06
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#define CEC_TX_MSG_7_OP6 0x07
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#define CEC_TX_MSG_8_OP7 0x08
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#define CEC_TX_MSG_9_OP8 0x09
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#define CEC_TX_MSG_A_OP9 0x0A
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#define CEC_TX_MSG_B_OP10 0x0B
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#define CEC_TX_MSG_C_OP11 0x0C
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#define CEC_TX_MSG_D_OP12 0x0D
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#define CEC_TX_MSG_E_OP13 0x0E
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#define CEC_TX_MSG_F_OP14 0x0F
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#define CEC_TX_MSG_LENGTH 0x10
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#define CEC_TX_MSG_CMD 0x11
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#define CEC_TX_WRITE_BUF 0x12
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#define CEC_TX_CLEAR_BUF 0x13
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#define CEC_RX_MSG_CMD 0x14
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#define CEC_RX_CLEAR_BUF 0x15
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#define CEC_LOGICAL_ADDR0 0x16
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#define CEC_LOGICAL_ADDR1 0x17
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#define CEC_LOGICAL_ADDR2 0x18
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#define CEC_LOGICAL_ADDR3 0x19
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#define CEC_LOGICAL_ADDR4 0x1A
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#define CEC_CLOCK_DIV_H 0x1B
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#define CEC_CLOCK_DIV_L 0x1C
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#define CEC_QUIESCENT_25MS_BIT7_0 0x20
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#define CEC_QUIESCENT_25MS_BIT11_8 0x21
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#define CEC_STARTBITMINL2H_3MS5_BIT7_0 0x22
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#define CEC_STARTBITMINL2H_3MS5_BIT8 0x23
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#define CEC_STARTBITMAXL2H_3MS9_BIT7_0 0x24
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#define CEC_STARTBITMAXL2H_3MS9_BIT8 0x25
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#define CEC_STARTBITMINH_0MS6_BIT7_0 0x26
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#define CEC_STARTBITMINH_0MS6_BIT8 0x27
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#define CEC_STARTBITMAXH_1MS0_BIT7_0 0x28
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#define CEC_STARTBITMAXH_1MS0_BIT8 0x29
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#define CEC_STARTBITMINTOT_4MS3_BIT7_0 0x2A
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#define CEC_STARTBITMINTOT_4MS3_BIT9_8 0x2B
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#define CEC_STARTBITMAXTOT_4MS7_BIT7_0 0x2C
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#define CEC_STARTBITMAXTOT_4MS7_BIT9_8 0x2D
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#define CEC_LOGIC1MINL2H_0MS4_BIT7_0 0x2E
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#define CEC_LOGIC1MINL2H_0MS4_BIT8 0x2F
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#define CEC_LOGIC1MAXL2H_0MS8_BIT7_0 0x30
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#define CEC_LOGIC1MAXL2H_0MS8_BIT8 0x31
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#define CEC_LOGIC0MINL2H_1MS3_BIT7_0 0x32
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#define CEC_LOGIC0MINL2H_1MS3_BIT8 0x33
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#define CEC_LOGIC0MAXL2H_1MS7_BIT7_0 0x34
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#define CEC_LOGIC0MAXL2H_1MS7_BIT8 0x35
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#define CEC_LOGICMINTOTAL_2MS05_BIT7_0 0x36
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#define CEC_LOGICMINTOTAL_2MS05_BIT9_8 0x37
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#define CEC_LOGICMAXHIGH_2MS8_BIT7_0 0x38
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#define CEC_LOGICMAXHIGH_2MS8_BIT8 0x39
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#define CEC_LOGICERRLOW_3MS4_BIT7_0 0x3A
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#define CEC_LOGICERRLOW_3MS4_BIT8 0x3B
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#define CEC_NOMSMPPOINT_1MS05 0x3C
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#define CEC_DELCNTR_LOGICERR 0x3E
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#define CEC_TXTIME_17MS_BIT7_0 0x40
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#define CEC_TXTIME_17MS_BIT10_8 0x41
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#define CEC_TXTIME_2BIT_BIT7_0 0x42
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#define CEC_TXTIME_2BIT_BIT10_8 0x43
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#define CEC_TXTIME_4BIT_BIT7_0 0x44
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#define CEC_TXTIME_4BIT_BIT10_8 0x45
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#define CEC_STARTBITNOML2H_3MS7_BIT7_0 0x46
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#define CEC_STARTBITNOML2H_3MS7_BIT8 0x47
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#define CEC_STARTBITNOMH_0MS8_BIT7_0 0x48
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#define CEC_STARTBITNOMH_0MS8_BIT8 0x49
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#define CEC_LOGIC1NOML2H_0MS6_BIT7_0 0x4A
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#define CEC_LOGIC1NOML2H_0MS6_BIT8 0x4B
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#define CEC_LOGIC0NOML2H_1MS5_BIT7_0 0x4C
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#define CEC_LOGIC0NOML2H_1MS5_BIT8 0x4D
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#define CEC_LOGIC1NOMH_1MS8_BIT7_0 0x4E
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#define CEC_LOGIC1NOMH_1MS8_BIT8 0x4F
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#define CEC_LOGIC0NOMH_0MS9_BIT7_0 0x50
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#define CEC_LOGIC0NOMH_0MS9_BIT8 0x51
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#define CEC_LOGICERRLOW_3MS6_BIT7_0 0x52
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#define CEC_LOGICERRLOW_3MS6_BIT8 0x53
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#define CEC_CHKCONTENTION_0MS1 0x54
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#define CEC_PREPARENXTBIT_0MS05_BIT7_0 0x56
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#define CEC_PREPARENXTBIT_0MS05_BIT8 0x57
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#define CEC_NOMSMPACKPOINT_0MS45 0x58
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#define CEC_ACK0NOML2H_1MS5_BIT7_0 0x5A
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#define CEC_ACK0NOML2H_1MS5_BIT8 0x5B
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#define CEC_BUGFIX_DISABLE_0 0x60
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#define CEC_BUGFIX_DISABLE_1 0x61
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#define CEC_RX_MSG_0_HEADER 0x80
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#define CEC_RX_MSG_1_OPCODE 0x81
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#define CEC_RX_MSG_2_OP1 0x82
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#define CEC_RX_MSG_3_OP2 0x83
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#define CEC_RX_MSG_4_OP3 0x84
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#define CEC_RX_MSG_5_OP4 0x85
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#define CEC_RX_MSG_6_OP5 0x86
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#define CEC_RX_MSG_7_OP6 0x87
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#define CEC_RX_MSG_8_OP7 0x88
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#define CEC_RX_MSG_9_OP8 0x89
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#define CEC_RX_MSG_A_OP9 0x8A
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#define CEC_RX_MSG_B_OP10 0x8B
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#define CEC_RX_MSG_C_OP11 0x8C
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#define CEC_RX_MSG_D_OP12 0x8D
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#define CEC_RX_MSG_E_OP13 0x8E
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#define CEC_RX_MSG_F_OP14 0x8F
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#define CEC_RX_MSG_LENGTH 0x90
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#define CEC_RX_MSG_STATUS 0x91
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#define CEC_RX_NUM_MSG 0x92
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#define CEC_TX_MSG_STATUS 0x93
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#define CEC_TX_NUM_MSG 0x94
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/* CEC_TX_MSG_CMD definition */
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#define TX_NO_OP 0 /* No transaction */
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#define TX_REQ_CURRENT 1 /* Transmit earliest message in buffer */
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#define TX_ABORT 2 /* Abort transmitting earliest message */
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#define TX_REQ_NEXT 3 /* Overwrite earliest msg, transmit next */
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/* tx_msg_status definition */
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#define TX_IDLE 0 /* No transaction */
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#define TX_BUSY 1 /* Transmitter is busy */
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#define TX_DONE 2 /* Message successfully transmitted */
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#define TX_ERROR 3 /* Message transmitted with error */
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/* rx_msg_cmd */
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#define RX_NO_OP 0 /* No transaction */
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#define RX_ACK_CURRENT 1 /* Read earliest message in buffer */
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#define RX_DISABLE 2 /* Disable receiving latest message */
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#define RX_ACK_NEXT 3 /* Clear earliest msg, read next */
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/* rx_msg_status */
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#define RX_IDLE 0 /* No transaction */
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#define RX_BUSY 1 /* Receiver is busy */
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#define RX_DONE 2 /* Message has been received successfully */
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#define RX_ERROR 3 /* Message has been received with error */
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/* RX_CLEAR_BUF options */
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#define CLEAR_START 1
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#define CLEAR_STOP 0
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/* CEC_LOGICAL_ADDRx options */
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#define LOGICAL_ADDR_MASK 0xf
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#define LOGICAL_ADDR_VALID BIT(4)
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#define LOGICAL_ADDR_DISABLE 0
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#define CEC_CLK_RATE 32768
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struct meson_ao_cec_device {
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struct platform_device *pdev;
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void __iomem *base;
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struct clk *core;
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spinlock_t cec_reg_lock;
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struct cec_notifier *notify;
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struct cec_adapter *adap;
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struct cec_msg rx_msg;
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};
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#define writel_bits_relaxed(mask, val, addr) \
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writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
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static inline int meson_ao_cec_wait_busy(struct meson_ao_cec_device *ao_cec)
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{
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ktime_t timeout = ktime_add_us(ktime_get(), 5000);
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while (readl_relaxed(ao_cec->base + CEC_RW_REG) & CEC_RW_BUS_BUSY) {
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if (ktime_compare(ktime_get(), timeout) > 0)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void meson_ao_cec_read(struct meson_ao_cec_device *ao_cec,
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unsigned long address, u8 *data,
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int *res)
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{
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unsigned long flags;
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u32 reg = FIELD_PREP(CEC_RW_ADDR, address);
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int ret = 0;
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if (res && *res)
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return;
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spin_lock_irqsave(&ao_cec->cec_reg_lock, flags);
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ret = meson_ao_cec_wait_busy(ao_cec);
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if (ret)
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goto read_out;
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writel_relaxed(reg, ao_cec->base + CEC_RW_REG);
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ret = meson_ao_cec_wait_busy(ao_cec);
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if (ret)
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goto read_out;
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*data = FIELD_GET(CEC_RW_RD_DATA,
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readl_relaxed(ao_cec->base + CEC_RW_REG));
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read_out:
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spin_unlock_irqrestore(&ao_cec->cec_reg_lock, flags);
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if (res)
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*res = ret;
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}
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static void meson_ao_cec_write(struct meson_ao_cec_device *ao_cec,
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unsigned long address, u8 data,
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int *res)
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{
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unsigned long flags;
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u32 reg = FIELD_PREP(CEC_RW_ADDR, address) |
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FIELD_PREP(CEC_RW_WR_DATA, data) |
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CEC_RW_WRITE_EN;
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int ret = 0;
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if (res && *res)
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return;
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spin_lock_irqsave(&ao_cec->cec_reg_lock, flags);
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ret = meson_ao_cec_wait_busy(ao_cec);
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if (ret)
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goto write_out;
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writel_relaxed(reg, ao_cec->base + CEC_RW_REG);
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write_out:
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spin_unlock_irqrestore(&ao_cec->cec_reg_lock, flags);
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if (res)
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*res = ret;
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}
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static inline void meson_ao_cec_irq_setup(struct meson_ao_cec_device *ao_cec,
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bool enable)
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{
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u32 cfg = CEC_INTR_TX | CEC_INTR_RX;
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writel_bits_relaxed(cfg, enable ? cfg : 0,
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ao_cec->base + CEC_INTR_MASKN_REG);
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}
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static inline int meson_ao_cec_clear(struct meson_ao_cec_device *ao_cec)
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{
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int ret = 0;
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meson_ao_cec_write(ao_cec, CEC_RX_MSG_CMD, RX_DISABLE, &ret);
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meson_ao_cec_write(ao_cec, CEC_TX_MSG_CMD, TX_ABORT, &ret);
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meson_ao_cec_write(ao_cec, CEC_RX_CLEAR_BUF, 1, &ret);
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meson_ao_cec_write(ao_cec, CEC_TX_CLEAR_BUF, 1, &ret);
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if (ret)
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return ret;
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udelay(100);
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meson_ao_cec_write(ao_cec, CEC_RX_CLEAR_BUF, 0, &ret);
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meson_ao_cec_write(ao_cec, CEC_TX_CLEAR_BUF, 0, &ret);
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if (ret)
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return ret;
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udelay(100);
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meson_ao_cec_write(ao_cec, CEC_RX_MSG_CMD, RX_NO_OP, &ret);
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meson_ao_cec_write(ao_cec, CEC_TX_MSG_CMD, TX_NO_OP, &ret);
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return ret;
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}
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static int meson_ao_cec_arbit_bit_time_set(struct meson_ao_cec_device *ao_cec,
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unsigned int bit_set,
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unsigned int time_set)
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{
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int ret = 0;
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switch (bit_set) {
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case CEC_SIGNAL_FREE_TIME_RETRY:
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meson_ao_cec_write(ao_cec, CEC_TXTIME_4BIT_BIT7_0,
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time_set & 0xff, &ret);
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meson_ao_cec_write(ao_cec, CEC_TXTIME_4BIT_BIT10_8,
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(time_set >> 8) & 0x7, &ret);
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break;
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case CEC_SIGNAL_FREE_TIME_NEW_INITIATOR:
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meson_ao_cec_write(ao_cec, CEC_TXTIME_2BIT_BIT7_0,
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time_set & 0xff, &ret);
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meson_ao_cec_write(ao_cec, CEC_TXTIME_2BIT_BIT10_8,
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(time_set >> 8) & 0x7, &ret);
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break;
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case CEC_SIGNAL_FREE_TIME_NEXT_XFER:
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meson_ao_cec_write(ao_cec, CEC_TXTIME_17MS_BIT7_0,
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time_set & 0xff, &ret);
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meson_ao_cec_write(ao_cec, CEC_TXTIME_17MS_BIT10_8,
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(time_set >> 8) & 0x7, &ret);
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break;
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}
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return ret;
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}
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static irqreturn_t meson_ao_cec_irq(int irq, void *data)
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{
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struct meson_ao_cec_device *ao_cec = data;
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u32 stat = readl_relaxed(ao_cec->base + CEC_INTR_STAT_REG);
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if (stat)
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return IRQ_WAKE_THREAD;
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return IRQ_NONE;
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}
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static void meson_ao_cec_irq_tx(struct meson_ao_cec_device *ao_cec)
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{
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unsigned long tx_status = 0;
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u8 stat;
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int ret = 0;
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meson_ao_cec_read(ao_cec, CEC_TX_MSG_STATUS, &stat, &ret);
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if (ret)
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goto tx_reg_err;
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switch (stat) {
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case TX_DONE:
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tx_status = CEC_TX_STATUS_OK;
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break;
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case TX_BUSY:
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tx_status = CEC_TX_STATUS_ARB_LOST;
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break;
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case TX_IDLE:
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tx_status = CEC_TX_STATUS_LOW_DRIVE;
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break;
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case TX_ERROR:
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default:
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tx_status = CEC_TX_STATUS_NACK;
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break;
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}
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/* Clear Interruption */
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writel_relaxed(CEC_INTR_TX, ao_cec->base + CEC_INTR_CLR_REG);
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/* Stop TX */
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meson_ao_cec_write(ao_cec, CEC_TX_MSG_CMD, TX_NO_OP, &ret);
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if (ret)
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goto tx_reg_err;
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cec_transmit_attempt_done(ao_cec->adap, tx_status);
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return;
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tx_reg_err:
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cec_transmit_attempt_done(ao_cec->adap, CEC_TX_STATUS_ERROR);
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}
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static void meson_ao_cec_irq_rx(struct meson_ao_cec_device *ao_cec)
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{
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int i, ret = 0;
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u8 reg;
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|
|
meson_ao_cec_read(ao_cec, CEC_RX_MSG_STATUS, ®, &ret);
|
|
if (reg != RX_DONE)
|
|
goto rx_out;
|
|
|
|
meson_ao_cec_read(ao_cec, CEC_RX_NUM_MSG, ®, &ret);
|
|
if (reg != 1)
|
|
goto rx_out;
|
|
|
|
meson_ao_cec_read(ao_cec, CEC_RX_MSG_LENGTH, ®, &ret);
|
|
|
|
ao_cec->rx_msg.len = reg + 1;
|
|
if (ao_cec->rx_msg.len > CEC_MAX_MSG_SIZE)
|
|
ao_cec->rx_msg.len = CEC_MAX_MSG_SIZE;
|
|
|
|
for (i = 0; i < ao_cec->rx_msg.len; i++) {
|
|
u8 byte;
|
|
|
|
meson_ao_cec_read(ao_cec, CEC_RX_MSG_0_HEADER + i, &byte, &ret);
|
|
|
|
ao_cec->rx_msg.msg[i] = byte;
|
|
}
|
|
|
|
if (ret)
|
|
goto rx_out;
|
|
|
|
cec_received_msg(ao_cec->adap, &ao_cec->rx_msg);
|
|
|
|
rx_out:
|
|
/* Clear Interruption */
|
|
writel_relaxed(CEC_INTR_RX, ao_cec->base + CEC_INTR_CLR_REG);
|
|
|
|
/* Ack RX message */
|
|
meson_ao_cec_write(ao_cec, CEC_RX_MSG_CMD, RX_ACK_CURRENT, &ret);
|
|
meson_ao_cec_write(ao_cec, CEC_RX_MSG_CMD, RX_NO_OP, &ret);
|
|
|
|
/* Clear RX buffer */
|
|
meson_ao_cec_write(ao_cec, CEC_RX_CLEAR_BUF, CLEAR_START, &ret);
|
|
meson_ao_cec_write(ao_cec, CEC_RX_CLEAR_BUF, CLEAR_STOP, &ret);
|
|
}
|
|
|
|
static irqreturn_t meson_ao_cec_irq_thread(int irq, void *data)
|
|
{
|
|
struct meson_ao_cec_device *ao_cec = data;
|
|
u32 stat = readl_relaxed(ao_cec->base + CEC_INTR_STAT_REG);
|
|
|
|
if (stat & CEC_INTR_TX)
|
|
meson_ao_cec_irq_tx(ao_cec);
|
|
|
|
meson_ao_cec_irq_rx(ao_cec);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int meson_ao_cec_set_log_addr(struct cec_adapter *adap, u8 logical_addr)
|
|
{
|
|
struct meson_ao_cec_device *ao_cec = adap->priv;
|
|
int ret = 0;
|
|
|
|
meson_ao_cec_write(ao_cec, CEC_LOGICAL_ADDR0,
|
|
LOGICAL_ADDR_DISABLE, &ret);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = meson_ao_cec_clear(ao_cec);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (logical_addr == CEC_LOG_ADDR_INVALID)
|
|
return 0;
|
|
|
|
meson_ao_cec_write(ao_cec, CEC_LOGICAL_ADDR0,
|
|
logical_addr & LOGICAL_ADDR_MASK, &ret);
|
|
if (ret)
|
|
return ret;
|
|
|
|
udelay(100);
|
|
|
|
meson_ao_cec_write(ao_cec, CEC_LOGICAL_ADDR0,
|
|
(logical_addr & LOGICAL_ADDR_MASK) |
|
|
LOGICAL_ADDR_VALID, &ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_ao_cec_transmit(struct cec_adapter *adap, u8 attempts,
|
|
u32 signal_free_time, struct cec_msg *msg)
|
|
{
|
|
struct meson_ao_cec_device *ao_cec = adap->priv;
|
|
int i, ret = 0;
|
|
u8 reg;
|
|
|
|
meson_ao_cec_read(ao_cec, CEC_TX_MSG_STATUS, ®, &ret);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (reg == TX_BUSY) {
|
|
dev_dbg(&ao_cec->pdev->dev, "%s: busy TX: aborting\n",
|
|
__func__);
|
|
meson_ao_cec_write(ao_cec, CEC_TX_MSG_CMD, TX_ABORT, &ret);
|
|
}
|
|
|
|
for (i = 0; i < msg->len; i++) {
|
|
meson_ao_cec_write(ao_cec, CEC_TX_MSG_0_HEADER + i,
|
|
msg->msg[i], &ret);
|
|
}
|
|
|
|
meson_ao_cec_write(ao_cec, CEC_TX_MSG_LENGTH, msg->len - 1, &ret);
|
|
meson_ao_cec_write(ao_cec, CEC_TX_MSG_CMD, TX_REQ_CURRENT, &ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_ao_cec_adap_enable(struct cec_adapter *adap, bool enable)
|
|
{
|
|
struct meson_ao_cec_device *ao_cec = adap->priv;
|
|
int ret;
|
|
|
|
meson_ao_cec_irq_setup(ao_cec, false);
|
|
|
|
writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET,
|
|
ao_cec->base + CEC_GEN_CNTL_REG);
|
|
|
|
if (!enable)
|
|
return 0;
|
|
|
|
/* Enable gated clock (Normal mode). */
|
|
writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK,
|
|
FIELD_PREP(CEC_GEN_CNTL_CLK_CTRL_MASK,
|
|
CEC_GEN_CNTL_CLK_ENABLE),
|
|
ao_cec->base + CEC_GEN_CNTL_REG);
|
|
|
|
udelay(100);
|
|
|
|
/* Release Reset */
|
|
writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0,
|
|
ao_cec->base + CEC_GEN_CNTL_REG);
|
|
|
|
/* Clear buffers */
|
|
ret = meson_ao_cec_clear(ao_cec);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* CEC arbitration 3/5/7 bit time set. */
|
|
ret = meson_ao_cec_arbit_bit_time_set(ao_cec,
|
|
CEC_SIGNAL_FREE_TIME_RETRY,
|
|
0x118);
|
|
if (ret)
|
|
return ret;
|
|
ret = meson_ao_cec_arbit_bit_time_set(ao_cec,
|
|
CEC_SIGNAL_FREE_TIME_NEW_INITIATOR,
|
|
0x000);
|
|
if (ret)
|
|
return ret;
|
|
ret = meson_ao_cec_arbit_bit_time_set(ao_cec,
|
|
CEC_SIGNAL_FREE_TIME_NEXT_XFER,
|
|
0x2aa);
|
|
if (ret)
|
|
return ret;
|
|
|
|
meson_ao_cec_irq_setup(ao_cec, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct cec_adap_ops meson_ao_cec_ops = {
|
|
.adap_enable = meson_ao_cec_adap_enable,
|
|
.adap_log_addr = meson_ao_cec_set_log_addr,
|
|
.adap_transmit = meson_ao_cec_transmit,
|
|
};
|
|
|
|
static int meson_ao_cec_probe(struct platform_device *pdev)
|
|
{
|
|
struct meson_ao_cec_device *ao_cec;
|
|
struct device *hdmi_dev;
|
|
struct resource *res;
|
|
int ret, irq;
|
|
|
|
hdmi_dev = cec_notifier_parse_hdmi_phandle(&pdev->dev);
|
|
|
|
if (IS_ERR(hdmi_dev))
|
|
return PTR_ERR(hdmi_dev);
|
|
|
|
ao_cec = devm_kzalloc(&pdev->dev, sizeof(*ao_cec), GFP_KERNEL);
|
|
if (!ao_cec)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&ao_cec->cec_reg_lock);
|
|
|
|
ao_cec->adap = cec_allocate_adapter(&meson_ao_cec_ops, ao_cec,
|
|
"meson_ao_cec",
|
|
CEC_CAP_DEFAULTS |
|
|
CEC_CAP_CONNECTOR_INFO,
|
|
1); /* Use 1 for now */
|
|
if (IS_ERR(ao_cec->adap))
|
|
return PTR_ERR(ao_cec->adap);
|
|
|
|
ao_cec->adap->owner = THIS_MODULE;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
ao_cec->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(ao_cec->base)) {
|
|
ret = PTR_ERR(ao_cec->base);
|
|
goto out_probe_adapter;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
ret = devm_request_threaded_irq(&pdev->dev, irq,
|
|
meson_ao_cec_irq,
|
|
meson_ao_cec_irq_thread,
|
|
0, NULL, ao_cec);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "irq request failed\n");
|
|
goto out_probe_adapter;
|
|
}
|
|
|
|
ao_cec->core = devm_clk_get(&pdev->dev, "core");
|
|
if (IS_ERR(ao_cec->core)) {
|
|
dev_err(&pdev->dev, "core clock request failed\n");
|
|
ret = PTR_ERR(ao_cec->core);
|
|
goto out_probe_adapter;
|
|
}
|
|
|
|
ret = clk_prepare_enable(ao_cec->core);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "core clock enable failed\n");
|
|
goto out_probe_adapter;
|
|
}
|
|
|
|
ret = clk_set_rate(ao_cec->core, CEC_CLK_RATE);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "core clock set rate failed\n");
|
|
goto out_probe_clk;
|
|
}
|
|
|
|
device_reset_optional(&pdev->dev);
|
|
|
|
ao_cec->pdev = pdev;
|
|
platform_set_drvdata(pdev, ao_cec);
|
|
|
|
ao_cec->notify = cec_notifier_cec_adap_register(hdmi_dev, NULL,
|
|
ao_cec->adap);
|
|
if (!ao_cec->notify) {
|
|
ret = -ENOMEM;
|
|
goto out_probe_clk;
|
|
}
|
|
|
|
ret = cec_register_adapter(ao_cec->adap, &pdev->dev);
|
|
if (ret < 0)
|
|
goto out_probe_notify;
|
|
|
|
/* Setup Hardware */
|
|
writel_relaxed(CEC_GEN_CNTL_RESET,
|
|
ao_cec->base + CEC_GEN_CNTL_REG);
|
|
|
|
return 0;
|
|
|
|
out_probe_notify:
|
|
cec_notifier_cec_adap_unregister(ao_cec->notify, ao_cec->adap);
|
|
|
|
out_probe_clk:
|
|
clk_disable_unprepare(ao_cec->core);
|
|
|
|
out_probe_adapter:
|
|
cec_delete_adapter(ao_cec->adap);
|
|
|
|
dev_err(&pdev->dev, "CEC controller registration failed\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int meson_ao_cec_remove(struct platform_device *pdev)
|
|
{
|
|
struct meson_ao_cec_device *ao_cec = platform_get_drvdata(pdev);
|
|
|
|
clk_disable_unprepare(ao_cec->core);
|
|
|
|
cec_notifier_cec_adap_unregister(ao_cec->notify, ao_cec->adap);
|
|
cec_unregister_adapter(ao_cec->adap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id meson_ao_cec_of_match[] = {
|
|
{ .compatible = "amlogic,meson-gx-ao-cec", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, meson_ao_cec_of_match);
|
|
|
|
static struct platform_driver meson_ao_cec_driver = {
|
|
.probe = meson_ao_cec_probe,
|
|
.remove = meson_ao_cec_remove,
|
|
.driver = {
|
|
.name = "meson-ao-cec",
|
|
.of_match_table = of_match_ptr(meson_ao_cec_of_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(meson_ao_cec_driver);
|
|
|
|
MODULE_DESCRIPTION("Meson AO CEC Controller driver");
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
MODULE_LICENSE("GPL");
|