OpenCloudOS-Kernel/drivers/pmdomain
Taniya Das f0cc5f7cb4 pmdomain: qcom: rpmhpd: Skip retention level for Power Domains
commit ddab91f4b2de5c5b46e312a90107d9353087d8ea upstream.

In the cases where the power domain connected to logics is allowed to
transition from a level(L)-->power collapse(0)-->retention(1) or
vice versa retention(1)-->power collapse(0)-->level(L)  will cause the
logic to lose the configurations. The ARC does not support retention
to collapse transition on MxC rails.

The targets from SM8450 onwards the PLL logics of clock controllers are
connected to MxC rails and the recommended configurations are carried
out during the clock controller probes. The MxC transition as mentioned
above should be skipped to ensure the PLL settings are intact across
clock controller power on & off.

On older targets that do not split MX into MxA and MxC does not collapse
the logic and it is parked always at RETENTION, thus this issue is never
observed on those targets.

Cc: stable@vger.kernel.org # v5.17
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240625-avoid_mxc_retention-v2-1-af9c2f549a5f@quicinc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-07-18 13:21:22 +02:00
..
actions
amlogic pmdomain: amlogic: Fix mask for the second NNA mem PD domain 2023-11-28 17:20:00 +00:00
apple
bcm pmdomain: bcm: bcm2835-power: check if the ASB register is equal to enable 2023-11-28 17:19:59 +00:00
imx pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix domain 2024-04-13 13:07:30 +02:00
mediatek pmdomain: mediatek: fix race conditions with genpd 2024-02-23 09:25:07 +01:00
qcom pmdomain: qcom: rpmhpd: Skip retention level for Power Domains 2024-07-18 13:21:22 +02:00
renesas pmdomain: renesas: r8a77980-sysc: CR7 must be always on 2024-02-23 09:25:15 +01:00
rockchip
samsung
st
starfive
sunxi
tegra
ti pmdomain: ti-sci: Fix duplicate PD referrals 2024-06-21 14:38:44 +02:00
xilinx
Makefile