409 lines
12 KiB
C
409 lines
12 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2018 Intel Corp
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*
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* Author:
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* Manasi Navare <manasi.d.navare@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/byteorder/generic.h>
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#include <drm/drm_print.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_dsc.h>
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/**
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* DOC: dsc helpers
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*
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* VESA specification for DP 1.4 adds a new feature called Display Stream
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* Compression (DSC) used to compress the pixel bits before sending it on
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* DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
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* display interfaces can support high resolutions at higher frames rates uisng
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* the maximum available link capacity of these interfaces.
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*
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* These functions contain some common logic and helpers to deal with VESA
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* Display Stream Compression standard required for DSC on Display Port/eDP or
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* MIPI display interfaces.
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*/
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/**
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* drm_dsc_dp_pps_header_init() - Initializes the PPS Header
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* for DisplayPort as per the DP 1.4 spec.
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* @pps_header: Secondary data packet header for DSC Picture
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* Parameter Set as defined in &struct dp_sdp_header
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*
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* DP 1.4 spec defines the secondary data packet for sending the
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* picture parameter infoframes from the source to the sink.
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* This function populates the SDP header defined in
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* &struct dp_sdp_header.
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*/
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void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header)
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{
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memset(pps_header, 0, sizeof(*pps_header));
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pps_header->HB1 = DP_SDP_PPS;
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pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
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}
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EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
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/**
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* drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
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* @rc_buffer_block_size: block size code, according to DPCD offset 62h
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* @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
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*
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* return:
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* buffer size in bytes, or 0 on invalid input
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*/
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int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size)
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{
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int size = 1024 * (rc_buffer_size + 1);
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switch (rc_buffer_block_size) {
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case DP_DSC_RC_BUF_BLK_SIZE_1:
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return 1 * size;
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case DP_DSC_RC_BUF_BLK_SIZE_4:
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return 4 * size;
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case DP_DSC_RC_BUF_BLK_SIZE_16:
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return 16 * size;
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case DP_DSC_RC_BUF_BLK_SIZE_64:
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return 64 * size;
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default:
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return 0;
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}
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}
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EXPORT_SYMBOL(drm_dsc_dp_rc_buffer_size);
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/**
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* drm_dsc_pps_payload_pack() - Populates the DSC PPS
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*
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* @pps_payload:
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* Bitwise struct for DSC Picture Parameter Set. This is defined
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* by &struct drm_dsc_picture_parameter_set
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* @dsc_cfg:
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* DSC Configuration data filled by driver as defined by
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* &struct drm_dsc_config
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*
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* DSC source device sends a picture parameter set (PPS) containing the
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* information required by the sink to decode the compressed frame. Driver
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* populates the DSC PPS struct using the DSC configuration parameters in
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* the order expected by the DSC Display Sink device. For the DSC, the sink
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* device expects the PPS payload in big endian format for fields
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* that span more than 1 byte.
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*/
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void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
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const struct drm_dsc_config *dsc_cfg)
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{
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int i;
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/* Protect against someone accidentally changing struct size */
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BUILD_BUG_ON(sizeof(*pps_payload) !=
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DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
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memset(pps_payload, 0, sizeof(*pps_payload));
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/* PPS 0 */
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pps_payload->dsc_version =
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dsc_cfg->dsc_version_minor |
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dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
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/* PPS 1, 2 is 0 */
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/* PPS 3 */
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pps_payload->pps_3 =
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dsc_cfg->line_buf_depth |
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dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
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/* PPS 4 */
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pps_payload->pps_4 =
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((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
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DSC_PPS_MSB_SHIFT) |
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dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
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dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
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dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
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dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
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/* PPS 5 */
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pps_payload->bits_per_pixel_low =
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(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
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/*
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* The DSC panel expects the PPS packet to have big endian format
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* for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
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* to big endian format. If format is little endian, it will swap
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* bytes to convert to Big endian else keep it unchanged.
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*/
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/* PPS 6, 7 */
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pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
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/* PPS 8, 9 */
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pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
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/* PPS 10, 11 */
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pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
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/* PPS 12, 13 */
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pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
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/* PPS 14, 15 */
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pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
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/* PPS 16 */
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pps_payload->initial_xmit_delay_high =
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((dsc_cfg->initial_xmit_delay &
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DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
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DSC_PPS_MSB_SHIFT);
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/* PPS 17 */
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pps_payload->initial_xmit_delay_low =
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(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
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/* PPS 18, 19 */
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pps_payload->initial_dec_delay =
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cpu_to_be16(dsc_cfg->initial_dec_delay);
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/* PPS 20 is 0 */
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/* PPS 21 */
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pps_payload->initial_scale_value =
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dsc_cfg->initial_scale_value;
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/* PPS 22, 23 */
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pps_payload->scale_increment_interval =
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cpu_to_be16(dsc_cfg->scale_increment_interval);
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/* PPS 24 */
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pps_payload->scale_decrement_interval_high =
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((dsc_cfg->scale_decrement_interval &
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DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
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DSC_PPS_MSB_SHIFT);
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/* PPS 25 */
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pps_payload->scale_decrement_interval_low =
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(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
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/* PPS 26[7:0], PPS 27[7:5] RESERVED */
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/* PPS 27 */
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pps_payload->first_line_bpg_offset =
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dsc_cfg->first_line_bpg_offset;
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/* PPS 28, 29 */
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pps_payload->nfl_bpg_offset =
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cpu_to_be16(dsc_cfg->nfl_bpg_offset);
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/* PPS 30, 31 */
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pps_payload->slice_bpg_offset =
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cpu_to_be16(dsc_cfg->slice_bpg_offset);
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/* PPS 32, 33 */
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pps_payload->initial_offset =
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cpu_to_be16(dsc_cfg->initial_offset);
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/* PPS 34, 35 */
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pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
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/* PPS 36 */
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pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
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/* PPS 37 */
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pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
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/* PPS 38, 39 */
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pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size);
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/* PPS 40 */
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pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
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/* PPS 41 */
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pps_payload->rc_quant_incr_limit0 =
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dsc_cfg->rc_quant_incr_limit0;
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/* PPS 42 */
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pps_payload->rc_quant_incr_limit1 =
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dsc_cfg->rc_quant_incr_limit1;
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/* PPS 43 */
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pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
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DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
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/* PPS 44 - 57 */
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for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
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pps_payload->rc_buf_thresh[i] =
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dsc_cfg->rc_buf_thresh[i];
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/* PPS 58 - 87 */
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/*
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* For DSC sink programming the RC Range parameter fields
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* are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
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*/
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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pps_payload->rc_range_parameters[i] =
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cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
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DSC_PPS_RC_RANGE_MINQP_SHIFT) |
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(dsc_cfg->rc_range_params[i].range_max_qp <<
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DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
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(dsc_cfg->rc_range_params[i].range_bpg_offset));
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}
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/* PPS 88 */
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pps_payload->native_422_420 = dsc_cfg->native_422 |
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dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
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/* PPS 89 */
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pps_payload->second_line_bpg_offset =
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dsc_cfg->second_line_bpg_offset;
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/* PPS 90, 91 */
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pps_payload->nsl_bpg_offset =
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cpu_to_be16(dsc_cfg->nsl_bpg_offset);
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/* PPS 92, 93 */
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pps_payload->second_line_offset_adj =
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cpu_to_be16(dsc_cfg->second_line_offset_adj);
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/* PPS 94 - 127 are O */
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}
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EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
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/**
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* drm_dsc_compute_rc_parameters() - Write rate control
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* parameters to the dsc configuration defined in
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* &struct drm_dsc_config in accordance with the DSC 1.2
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* specification. Some configuration fields must be present
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* beforehand.
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*
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* @vdsc_cfg:
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* DSC Configuration data partially filled by driver
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*/
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int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
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{
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unsigned long groups_per_line = 0;
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unsigned long groups_total = 0;
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unsigned long num_extra_mux_bits = 0;
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unsigned long slice_bits = 0;
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unsigned long hrd_delay = 0;
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unsigned long final_scale = 0;
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unsigned long rbs_min = 0;
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if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
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/* Number of groups used to code each line of a slice */
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groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
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DSC_RC_PIXELS_PER_GROUP);
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/* chunksize in Bytes */
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vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
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vdsc_cfg->bits_per_pixel,
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(8 * 16));
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} else {
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/* Number of groups used to code each line of a slice */
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groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
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DSC_RC_PIXELS_PER_GROUP);
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/* chunksize in Bytes */
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vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
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vdsc_cfg->bits_per_pixel,
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(8 * 16));
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}
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if (vdsc_cfg->convert_rgb)
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num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4)
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- 2);
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else if (vdsc_cfg->native_422)
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num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4) +
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3 * (4 * vdsc_cfg->bits_per_component) - 2;
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else
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num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
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(4 * vdsc_cfg->bits_per_component + 4) +
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2 * (4 * vdsc_cfg->bits_per_component) - 2;
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/* Number of bits in one Slice */
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slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
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while ((num_extra_mux_bits > 0) &&
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((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
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num_extra_mux_bits--;
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if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
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vdsc_cfg->initial_scale_value = groups_per_line + 8;
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/* scale_decrement_interval calculation according to DSC spec 1.11 */
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if (vdsc_cfg->initial_scale_value > 8)
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vdsc_cfg->scale_decrement_interval = groups_per_line /
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(vdsc_cfg->initial_scale_value - 8);
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else
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vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
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vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
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(vdsc_cfg->initial_xmit_delay *
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vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
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if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
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DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
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return -ERANGE;
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}
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final_scale = (vdsc_cfg->rc_model_size * 8) /
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(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
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if (vdsc_cfg->slice_height > 1)
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/*
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* NflBpgOffset is 16 bit value with 11 fractional bits
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* hence we multiply by 2^11 for preserving the
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* fractional part
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*/
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vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
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(vdsc_cfg->slice_height - 1));
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else
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vdsc_cfg->nfl_bpg_offset = 0;
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/* Number of groups used to code the entire slice */
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groups_total = groups_per_line * vdsc_cfg->slice_height;
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/* slice_bpg_offset is 16 bit value with 11 fractional bits */
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vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
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vdsc_cfg->initial_offset +
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num_extra_mux_bits) << 11),
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groups_total);
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if (final_scale > 9) {
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/*
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* ScaleIncrementInterval =
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* finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
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* as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
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* we need divide by 2^11 from pstDscCfg values
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*/
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vdsc_cfg->scale_increment_interval =
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(vdsc_cfg->final_offset * (1 << 11)) /
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((vdsc_cfg->nfl_bpg_offset +
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vdsc_cfg->slice_bpg_offset) *
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(final_scale - 9));
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} else {
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/*
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* If finalScaleValue is less than or equal to 9, a value of 0 should
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* be used to disable the scale increment at the end of the slice
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*/
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vdsc_cfg->scale_increment_interval = 0;
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}
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/*
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* DSC spec mentions that bits_per_pixel specifies the target
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* bits/pixel (bpp) rate that is used by the encoder,
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* in steps of 1/16 of a bit per pixel
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*/
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rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
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DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
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vdsc_cfg->bits_per_pixel, 16) +
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groups_per_line * vdsc_cfg->first_line_bpg_offset;
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hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
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vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
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vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
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return 0;
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}
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EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
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