168 lines
4.0 KiB
C
168 lines
4.0 KiB
C
/*
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* P1022 RDK board specific routines
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Based on p1022_ds.c
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <asm/div64.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/udbg.h>
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#include <asm/fsl_guts.h>
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#include "smp.h"
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#include "mpc85xx.h"
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
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/**
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* p1022rdk_set_monitor_port: switch the output to a different monitor port
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*/
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static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
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{
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if (port != FSL_DIU_PORT_DVI) {
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pr_err("p1022rdk: unsupported monitor port %i\n", port);
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return;
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}
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}
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/**
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* p1022rdk_set_pixel_clock: program the DIU's clock
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*
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* @pixclock: the wavelength, in picoseconds, of the clock
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*/
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void p1022rdk_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *guts_np = NULL;
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struct ccsr_guts __iomem *guts;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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/* Map the global utilities registers. */
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_np) {
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pr_err("p1022rdk: missing global utilties device node\n");
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return;
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}
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guts = of_iomap(guts_np, 0);
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of_node_put(guts_np);
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if (!guts) {
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pr_err("p1022rdk: could not map global utilties device\n");
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return;
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}
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/* Convert pixclock from a wavelength to a frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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/*
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* 'pxclk' is the ratio of the platform clock to the pixel clock.
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* This number is programmed into the CLKDVDR register, and the valid
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* range of values is 2-255.
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*/
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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pxclk = clamp_t(u32, pxclk, 2, 255);
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(&guts->clkdvdr,
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
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iounmap(guts);
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}
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/**
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* p1022rdk_valid_monitor_port: set the monitor port for sysfs
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*/
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enum fsl_diu_monitor_port
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p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port)
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{
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return FSL_DIU_PORT_DVI;
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}
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#endif
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void __init p1022_rdk_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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/*
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* Setup the architecture
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*/
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static void __init p1022_rdk_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("p1022_rdk_setup_arch()", 0);
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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diu_ops.set_monitor_port = p1022rdk_set_monitor_port;
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diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock;
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diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port;
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#endif
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mpc85xx_smp_init();
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fsl_pci_assign_primary();
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swiotlb_detect_4g();
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pr_info("Freescale / iVeia P1022 RDK reference board\n");
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}
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machine_arch_initcall(p1022_rdk, mpc85xx_common_publish_devices);
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machine_arch_initcall(p1022_rdk, swiotlb_setup_bus_notifier);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init p1022_rdk_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,p1022rdk");
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}
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define_machine(p1022_rdk) {
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.name = "P1022 RDK",
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.probe = p1022_rdk_probe,
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.setup_arch = p1022_rdk_setup_arch,
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.init_IRQ = p1022_rdk_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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