305 lines
6.3 KiB
C
305 lines
6.3 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2018 Intel Corporation
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*/
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#include "../i915_selftest.h"
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#include "igt_wedge_me.h"
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#include "mock_context.h"
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static struct drm_i915_gem_object *
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read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_object *result;
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struct i915_request *rq;
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struct i915_vma *vma;
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const u32 base = engine->mmio_base;
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u32 srm, *cs;
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int err;
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int i;
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result = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
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if (IS_ERR(result))
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return result;
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i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
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cs = i915_gem_object_pin_map(result, I915_MAP_WB);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto err_obj;
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}
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memset(cs, 0xc5, PAGE_SIZE);
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i915_gem_object_unpin_map(result);
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vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_obj;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
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if (err)
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goto err_obj;
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intel_runtime_pm_get(engine->i915);
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rq = i915_request_alloc(engine, ctx);
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intel_runtime_pm_put(engine->i915);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto err_pin;
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}
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err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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if (err)
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goto err_req;
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srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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if (INTEL_GEN(ctx->i915) >= 8)
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srm++;
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cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto err_req;
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}
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for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
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*cs++ = srm;
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*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
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*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
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*cs++ = 0;
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}
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intel_ring_advance(rq, cs);
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i915_gem_object_get(result);
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i915_gem_object_set_active_reference(result);
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i915_request_add(rq);
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i915_vma_unpin(vma);
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return result;
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err_req:
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i915_request_add(rq);
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err_pin:
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i915_vma_unpin(vma);
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err_obj:
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i915_gem_object_put(result);
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return ERR_PTR(err);
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}
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static u32 get_whitelist_reg(const struct whitelist *w, unsigned int i)
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{
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return i < w->count ? i915_mmio_reg_offset(w->reg[i]) : w->nopid;
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}
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static void print_results(const struct whitelist *w, const u32 *results)
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{
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unsigned int i;
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for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
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u32 expected = get_whitelist_reg(w, i);
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u32 actual = results[i];
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pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",
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i, expected, actual);
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}
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}
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static int check_whitelist(const struct whitelist *w,
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struct i915_gem_context *ctx,
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struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_object *results;
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struct igt_wedge_me wedge;
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u32 *vaddr;
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int err;
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int i;
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results = read_nonprivs(ctx, engine);
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if (IS_ERR(results))
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return PTR_ERR(results);
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err = 0;
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igt_wedge_on_timeout(&wedge, ctx->i915, HZ / 5) /* a safety net! */
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err = i915_gem_object_set_to_cpu_domain(results, false);
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if (i915_terminally_wedged(&ctx->i915->gpu_error))
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err = -EIO;
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if (err)
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goto out_put;
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vaddr = i915_gem_object_pin_map(results, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto out_put;
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}
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for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
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u32 expected = get_whitelist_reg(w, i);
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u32 actual = vaddr[i];
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if (expected != actual) {
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print_results(w, vaddr);
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pr_err("Invalid RING_NONPRIV[%d], expected 0x%08x, found 0x%08x\n",
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i, expected, actual);
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err = -EINVAL;
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break;
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}
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}
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i915_gem_object_unpin_map(results);
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out_put:
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i915_gem_object_put(results);
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return err;
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}
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static int do_device_reset(struct intel_engine_cs *engine)
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{
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i915_reset(engine->i915, ENGINE_MASK(engine->id), NULL);
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return 0;
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}
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static int do_engine_reset(struct intel_engine_cs *engine)
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{
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return i915_reset_engine(engine, NULL);
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}
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static int switch_to_scratch_context(struct intel_engine_cs *engine)
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{
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struct i915_gem_context *ctx;
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struct i915_request *rq;
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ctx = kernel_context(engine->i915);
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if (IS_ERR(ctx))
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return PTR_ERR(ctx);
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intel_runtime_pm_get(engine->i915);
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rq = i915_request_alloc(engine, ctx);
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intel_runtime_pm_put(engine->i915);
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kernel_context_close(ctx);
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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i915_request_add(rq);
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return 0;
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}
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static int check_whitelist_across_reset(struct intel_engine_cs *engine,
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int (*reset)(struct intel_engine_cs *),
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const struct whitelist *w,
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const char *name)
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{
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struct i915_gem_context *ctx;
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int err;
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ctx = kernel_context(engine->i915);
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if (IS_ERR(ctx))
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return PTR_ERR(ctx);
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err = check_whitelist(w, ctx, engine);
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if (err) {
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pr_err("Invalid whitelist *before* %s reset!\n", name);
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goto out;
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}
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err = switch_to_scratch_context(engine);
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if (err)
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goto out;
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err = reset(engine);
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if (err) {
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pr_err("%s reset failed\n", name);
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goto out;
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}
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err = check_whitelist(w, ctx, engine);
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if (err) {
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pr_err("Whitelist not preserved in context across %s reset!\n",
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name);
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goto out;
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}
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kernel_context_close(ctx);
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ctx = kernel_context(engine->i915);
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if (IS_ERR(ctx))
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return PTR_ERR(ctx);
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err = check_whitelist(w, ctx, engine);
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if (err) {
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pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
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name);
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goto out;
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}
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out:
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kernel_context_close(ctx);
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return err;
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}
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static int live_reset_whitelist(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine = i915->engine[RCS];
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struct i915_gpu_error *error = &i915->gpu_error;
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struct whitelist w;
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int err = 0;
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/* If we reset the gpu, we should not lose the RING_NONPRIV */
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if (!engine)
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return 0;
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if (!whitelist_build(engine, &w))
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return 0;
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pr_info("Checking %d whitelisted registers (RING_NONPRIV)\n", w.count);
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set_bit(I915_RESET_BACKOFF, &error->flags);
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set_bit(I915_RESET_ENGINE + engine->id, &error->flags);
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if (intel_has_reset_engine(i915)) {
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err = check_whitelist_across_reset(engine,
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do_engine_reset, &w,
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"engine");
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if (err)
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goto out;
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}
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if (intel_has_gpu_reset(i915)) {
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err = check_whitelist_across_reset(engine,
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do_device_reset, &w,
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"device");
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if (err)
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goto out;
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}
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out:
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clear_bit(I915_RESET_ENGINE + engine->id, &error->flags);
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clear_bit(I915_RESET_BACKOFF, &error->flags);
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return err;
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}
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int intel_workarounds_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(live_reset_whitelist),
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};
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int err;
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if (i915_terminally_wedged(&i915->gpu_error))
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return 0;
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mutex_lock(&i915->drm.struct_mutex);
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err = i915_subtests(tests, i915);
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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