151 lines
6.0 KiB
C
151 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
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* which was based on arch/arm/include/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2014 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_IO_H
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#define _ASM_RISCV_IO_H
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#include <linux/types.h>
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#include <asm/mmiowb.h>
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#include <asm/pgtable.h>
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/*
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* MMIO access functions are separated out to break dependency cycles
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* when using {read,write}* fns in low-level headers
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*/
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#include <asm/mmio.h>
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/*
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* I/O port access constants.
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*/
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#ifdef CONFIG_MMU
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#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
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#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
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#endif /* CONFIG_MMU */
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/*
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* Emulation routines for the port-mapped IO space used by some PCI drivers.
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* These are defined as being "fully synchronous", but also "not guaranteed to
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* be fully ordered with respect to other memory and I/O operations". We're
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* going to be on the safe side here and just make them:
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* - Fully ordered WRT each other, by bracketing them with two fences. The
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* outer set contains both I/O so inX is ordered with outX, while the inner just
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* needs the type of the access (I for inX and O for outX).
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* - Ordered in the same manner as readX/writeX WRT memory by subsuming their
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* fences.
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* - Ordered WRT timer reads, so udelay and friends don't get elided by the
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* implementation.
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* Note that there is no way to actually enforce that outX is a non-posted
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* operation on RISC-V, but hopefully the timer ordering constraint is
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* sufficient to ensure this works sanely on controllers that support I/O
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* writes.
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*/
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#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory");
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#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory");
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#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory");
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#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory");
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#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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#define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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#define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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#define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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#ifdef CONFIG_64BIT
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#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
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#define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
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#endif
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/*
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* Accesses from a single hart to a single I/O address must be ordered. This
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* allows us to use the raw read macros, but we still need to fence before and
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* after the block to ensure ordering WRT other macros. These are defined to
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* perform host-endian accesses so we use __raw instead of __cpu.
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*/
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#define __io_reads_ins(port, ctype, len, bfence, afence) \
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static inline void __ ## port ## len(const volatile void __iomem *addr, \
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void *buffer, \
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unsigned int count) \
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{ \
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bfence; \
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if (count) { \
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ctype *buf = buffer; \
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\
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do { \
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ctype x = __raw_read ## len(addr); \
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*buf++ = x; \
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} while (--count); \
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} \
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afence; \
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}
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#define __io_writes_outs(port, ctype, len, bfence, afence) \
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static inline void __ ## port ## len(volatile void __iomem *addr, \
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const void *buffer, \
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unsigned int count) \
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{ \
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bfence; \
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if (count) { \
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const ctype *buf = buffer; \
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\
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do { \
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__raw_write ## len(*buf++, addr); \
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} while (--count); \
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} \
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afence; \
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}
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__io_reads_ins(reads, u8, b, __io_br(), __io_ar(addr))
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__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
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__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
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#define readsb(addr, buffer, count) __readsb(addr, buffer, count)
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#define readsw(addr, buffer, count) __readsw(addr, buffer, count)
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#define readsl(addr, buffer, count) __readsl(addr, buffer, count)
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__io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
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__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
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__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
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#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
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#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
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#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
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__io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
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__io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
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__io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
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#define writesb(addr, buffer, count) __writesb(addr, buffer, count)
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#define writesw(addr, buffer, count) __writesw(addr, buffer, count)
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#define writesl(addr, buffer, count) __writesl(addr, buffer, count)
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__io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
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__io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
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__io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
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#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
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#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
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#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
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#ifdef CONFIG_64BIT
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__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
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#define readsq(addr, buffer, count) __readsq(addr, buffer, count)
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__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
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#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
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__io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
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#define writesq(addr, buffer, count) __writesq(addr, buffer, count)
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__io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
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#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
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#endif
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#include <asm-generic/io.h>
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#endif /* _ASM_RISCV_IO_H */
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