72 lines
2.0 KiB
C
72 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2017 Andes Technology Corporation */
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#ifndef _ASM_RISCV_FTRACE_H
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#define _ASM_RISCV_FTRACE_H
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/*
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* The graph frame test is not possible if CONFIG_FRAME_POINTER is not enabled.
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* Check arch/riscv/kernel/mcount.S for detail.
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*/
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#if defined(CONFIG_FUNCTION_GRAPH_TRACER) && defined(CONFIG_FRAME_POINTER)
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#define HAVE_FUNCTION_GRAPH_FP_TEST
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#endif
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#define HAVE_FUNCTION_GRAPH_RET_ADDR_PTR
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#define ARCH_SUPPORTS_FTRACE_OPS 1
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#ifndef __ASSEMBLY__
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void _mcount(void);
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static inline unsigned long ftrace_call_adjust(unsigned long addr)
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{
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return addr;
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}
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struct dyn_arch_ftrace {
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};
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#endif
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#ifdef CONFIG_DYNAMIC_FTRACE
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/*
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* A general call in RISC-V is a pair of insts:
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* 1) auipc: setting high-20 pc-related bits to ra register
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* 2) jalr: setting low-12 offset to ra, jump to ra, and set ra to
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* return address (original pc + 4)
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*
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* Dynamic ftrace generates probes to call sites, so we must deal with
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* both auipc and jalr at the same time.
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*/
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#define MCOUNT_ADDR ((unsigned long)_mcount)
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#define JALR_SIGN_MASK (0x00000800)
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#define JALR_OFFSET_MASK (0x00000fff)
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#define AUIPC_OFFSET_MASK (0xfffff000)
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#define AUIPC_PAD (0x00001000)
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#define JALR_SHIFT 20
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#define JALR_BASIC (0x000080e7)
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#define AUIPC_BASIC (0x00000097)
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#define NOP4 (0x00000013)
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#define make_call(caller, callee, call) \
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do { \
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call[0] = to_auipc_insn((unsigned int)((unsigned long)callee - \
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(unsigned long)caller)); \
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call[1] = to_jalr_insn((unsigned int)((unsigned long)callee - \
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(unsigned long)caller)); \
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} while (0)
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#define to_jalr_insn(offset) \
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(((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_BASIC)
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#define to_auipc_insn(offset) \
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((offset & JALR_SIGN_MASK) ? \
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(((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_BASIC) : \
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((offset & AUIPC_OFFSET_MASK) | AUIPC_BASIC))
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/*
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* Let auipc+jalr be the basic *mcount unit*, so we make it 8 bytes here.
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*/
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#define MCOUNT_INSN_SIZE 8
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#endif
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#endif /* _ASM_RISCV_FTRACE_H */
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