695 lines
18 KiB
C
695 lines
18 KiB
C
/*
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* Copyright (c) 2016-2017 NVIDIA Corporation
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*
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* Author: Thierry Reding <treding@nvidia.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/gpio/tegra194-gpio.h>
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#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
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#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
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#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
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#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
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#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
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#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
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#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
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#define TEGRA186_GPIO_INPUT 0x08
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#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
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#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
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#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
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#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
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#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
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#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
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#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
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struct tegra_gpio_port {
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const char *name;
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unsigned int offset;
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unsigned int pins;
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unsigned int irq;
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};
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struct tegra_gpio_soc {
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const struct tegra_gpio_port *ports;
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unsigned int num_ports;
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const char *name;
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};
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struct tegra_gpio {
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struct gpio_chip gpio;
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struct irq_chip intc;
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unsigned int num_irq;
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unsigned int *irq;
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const struct tegra_gpio_soc *soc;
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void __iomem *base;
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};
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static const struct tegra_gpio_port *
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tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
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{
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unsigned int start = 0, i;
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for (i = 0; i < gpio->soc->num_ports; i++) {
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const struct tegra_gpio_port *port = &gpio->soc->ports[i];
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if (*pin >= start && *pin < start + port->pins) {
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*pin -= start;
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return port;
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}
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start += port->pins;
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}
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return NULL;
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}
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static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
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unsigned int pin)
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{
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const struct tegra_gpio_port *port;
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port = tegra186_gpio_get_port(gpio, &pin);
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if (!port)
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return NULL;
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return gpio->base + port->offset + pin * 0x20;
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}
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static int tegra186_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, offset);
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if (WARN_ON(base == NULL))
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return -ENODEV;
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
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return 0;
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return 1;
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}
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static int tegra186_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, offset);
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if (WARN_ON(base == NULL))
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return -ENODEV;
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value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
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value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
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writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
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value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
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writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
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return 0;
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}
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static int tegra186_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int level)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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void __iomem *base;
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u32 value;
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/* configure output level first */
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chip->set(chip, offset, level);
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base = tegra186_gpio_get_base(gpio, offset);
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if (WARN_ON(base == NULL))
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return -EINVAL;
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/* set the direction */
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value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
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value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
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writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
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value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
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writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
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return 0;
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}
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static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, offset);
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if (WARN_ON(base == NULL))
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return -ENODEV;
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
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value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
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else
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value = readl(base + TEGRA186_GPIO_INPUT);
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return value & BIT(0);
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}
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static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int level)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, offset);
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if (WARN_ON(base == NULL))
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return;
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value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
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if (level == 0)
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value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
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else
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value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
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writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
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}
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static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
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const struct of_phandle_args *spec,
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u32 *flags)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(chip);
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unsigned int port, pin, i, offset = 0;
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if (WARN_ON(chip->of_gpio_n_cells < 2))
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return -EINVAL;
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if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
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return -EINVAL;
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port = spec->args[0] / 8;
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pin = spec->args[0] % 8;
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if (port >= gpio->soc->num_ports) {
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dev_err(chip->parent, "invalid port number: %u\n", port);
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return -EINVAL;
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}
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for (i = 0; i < port; i++)
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offset += gpio->soc->ports[i].pins;
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if (flags)
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*flags = spec->args[1];
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return offset + pin;
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}
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static void tegra186_irq_ack(struct irq_data *data)
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{
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struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
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void __iomem *base;
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base = tegra186_gpio_get_base(gpio, data->hwirq);
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if (WARN_ON(base == NULL))
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return;
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writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
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}
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static void tegra186_irq_mask(struct irq_data *data)
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{
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struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, data->hwirq);
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if (WARN_ON(base == NULL))
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return;
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
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writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
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}
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static void tegra186_irq_unmask(struct irq_data *data)
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{
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struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, data->hwirq);
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if (WARN_ON(base == NULL))
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return;
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
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writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
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}
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static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
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void __iomem *base;
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u32 value;
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base = tegra186_gpio_get_base(gpio, data->hwirq);
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if (WARN_ON(base == NULL))
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return -ENODEV;
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value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
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value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
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value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_NONE:
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break;
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case IRQ_TYPE_EDGE_RISING:
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
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break;
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default:
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return -EINVAL;
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}
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writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
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if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
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irq_set_handler_locked(data, handle_level_irq);
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else
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irq_set_handler_locked(data, handle_edge_irq);
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return 0;
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}
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static void tegra186_gpio_irq(struct irq_desc *desc)
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{
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struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
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struct irq_domain *domain = gpio->gpio.irq.domain;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int parent = irq_desc_get_irq(desc);
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unsigned int i, offset = 0;
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chained_irq_enter(chip, desc);
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for (i = 0; i < gpio->soc->num_ports; i++) {
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const struct tegra_gpio_port *port = &gpio->soc->ports[i];
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void __iomem *base = gpio->base + port->offset;
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unsigned int pin, irq;
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unsigned long value;
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/* skip ports that are not associated with this controller */
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if (parent != gpio->irq[port->irq])
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goto skip;
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value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
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for_each_set_bit(pin, &value, port->pins) {
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irq = irq_find_mapping(domain, offset + pin);
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if (WARN_ON(irq == 0))
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continue;
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generic_handle_irq(irq);
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}
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skip:
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offset += port->pins;
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}
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chained_irq_exit(chip, desc);
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}
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static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain,
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struct device_node *np,
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const u32 *spec, unsigned int size,
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unsigned long *hwirq,
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unsigned int *type)
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{
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struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
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unsigned int port, pin, i, offset = 0;
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if (size < 2)
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return -EINVAL;
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port = spec[0] / 8;
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pin = spec[0] % 8;
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if (port >= gpio->soc->num_ports) {
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dev_err(gpio->gpio.parent, "invalid port number: %u\n", port);
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return -EINVAL;
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}
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for (i = 0; i < port; i++)
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offset += gpio->soc->ports[i].pins;
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*type = spec[1] & IRQ_TYPE_SENSE_MASK;
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*hwirq = offset + pin;
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return 0;
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}
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static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = {
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.map = gpiochip_irq_map,
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.unmap = gpiochip_irq_unmap,
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.xlate = tegra186_gpio_irq_domain_xlate,
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};
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static int tegra186_gpio_probe(struct platform_device *pdev)
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{
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unsigned int i, j, offset;
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struct gpio_irq_chip *irq;
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struct tegra_gpio *gpio;
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struct resource *res;
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char **names;
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int err;
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gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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gpio->soc = of_device_get_match_data(&pdev->dev);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
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gpio->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gpio->base))
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return PTR_ERR(gpio->base);
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err = platform_irq_count(pdev);
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if (err < 0)
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return err;
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gpio->num_irq = err;
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gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
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GFP_KERNEL);
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if (!gpio->irq)
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return -ENOMEM;
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for (i = 0; i < gpio->num_irq; i++) {
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err = platform_get_irq(pdev, i);
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if (err < 0)
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return err;
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gpio->irq[i] = err;
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}
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gpio->gpio.label = gpio->soc->name;
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gpio->gpio.parent = &pdev->dev;
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gpio->gpio.get_direction = tegra186_gpio_get_direction;
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gpio->gpio.direction_input = tegra186_gpio_direction_input;
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gpio->gpio.direction_output = tegra186_gpio_direction_output;
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gpio->gpio.get = tegra186_gpio_get,
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gpio->gpio.set = tegra186_gpio_set;
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gpio->gpio.base = -1;
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for (i = 0; i < gpio->soc->num_ports; i++)
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gpio->gpio.ngpio += gpio->soc->ports[i].pins;
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names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
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sizeof(*names), GFP_KERNEL);
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if (!names)
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return -ENOMEM;
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for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
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const struct tegra_gpio_port *port = &gpio->soc->ports[i];
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char *name;
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for (j = 0; j < port->pins; j++) {
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name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
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"P%s.%02x", port->name, j);
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if (!name)
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return -ENOMEM;
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names[offset + j] = name;
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}
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offset += port->pins;
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}
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gpio->gpio.names = (const char * const *)names;
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gpio->gpio.of_node = pdev->dev.of_node;
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gpio->gpio.of_gpio_n_cells = 2;
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gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
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gpio->intc.name = pdev->dev.of_node->name;
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gpio->intc.irq_ack = tegra186_irq_ack;
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gpio->intc.irq_mask = tegra186_irq_mask;
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gpio->intc.irq_unmask = tegra186_irq_unmask;
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gpio->intc.irq_set_type = tegra186_irq_set_type;
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irq = &gpio->gpio.irq;
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irq->chip = &gpio->intc;
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irq->domain_ops = &tegra186_gpio_irq_domain_ops;
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irq->handler = handle_simple_irq;
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irq->default_type = IRQ_TYPE_NONE;
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irq->parent_handler = tegra186_gpio_irq;
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irq->parent_handler_data = gpio;
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irq->num_parents = gpio->num_irq;
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irq->parents = gpio->irq;
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irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
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sizeof(*irq->map), GFP_KERNEL);
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if (!irq->map)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
|
|
const struct tegra_gpio_port *port = &gpio->soc->ports[i];
|
|
|
|
for (j = 0; j < port->pins; j++)
|
|
irq->map[offset + j] = irq->parents[port->irq];
|
|
|
|
offset += port->pins;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, gpio);
|
|
|
|
err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra186_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#define TEGRA186_MAIN_GPIO_PORT(port, base, count, controller) \
|
|
[TEGRA186_MAIN_GPIO_PORT_##port] = { \
|
|
.name = #port, \
|
|
.offset = base, \
|
|
.pins = count, \
|
|
.irq = controller, \
|
|
}
|
|
|
|
static const struct tegra_gpio_port tegra186_main_ports[] = {
|
|
TEGRA186_MAIN_GPIO_PORT( A, 0x2000, 7, 2),
|
|
TEGRA186_MAIN_GPIO_PORT( B, 0x3000, 7, 3),
|
|
TEGRA186_MAIN_GPIO_PORT( C, 0x3200, 7, 3),
|
|
TEGRA186_MAIN_GPIO_PORT( D, 0x3400, 6, 3),
|
|
TEGRA186_MAIN_GPIO_PORT( E, 0x2200, 8, 2),
|
|
TEGRA186_MAIN_GPIO_PORT( F, 0x2400, 6, 2),
|
|
TEGRA186_MAIN_GPIO_PORT( G, 0x4200, 6, 4),
|
|
TEGRA186_MAIN_GPIO_PORT( H, 0x1000, 7, 1),
|
|
TEGRA186_MAIN_GPIO_PORT( I, 0x0800, 8, 0),
|
|
TEGRA186_MAIN_GPIO_PORT( J, 0x5000, 8, 5),
|
|
TEGRA186_MAIN_GPIO_PORT( K, 0x5200, 1, 5),
|
|
TEGRA186_MAIN_GPIO_PORT( L, 0x1200, 8, 1),
|
|
TEGRA186_MAIN_GPIO_PORT( M, 0x5600, 6, 5),
|
|
TEGRA186_MAIN_GPIO_PORT( N, 0x0000, 7, 0),
|
|
TEGRA186_MAIN_GPIO_PORT( O, 0x0200, 4, 0),
|
|
TEGRA186_MAIN_GPIO_PORT( P, 0x4000, 7, 4),
|
|
TEGRA186_MAIN_GPIO_PORT( Q, 0x0400, 6, 0),
|
|
TEGRA186_MAIN_GPIO_PORT( R, 0x0a00, 6, 0),
|
|
TEGRA186_MAIN_GPIO_PORT( T, 0x0600, 4, 0),
|
|
TEGRA186_MAIN_GPIO_PORT( X, 0x1400, 8, 1),
|
|
TEGRA186_MAIN_GPIO_PORT( Y, 0x1600, 7, 1),
|
|
TEGRA186_MAIN_GPIO_PORT(BB, 0x2600, 2, 2),
|
|
TEGRA186_MAIN_GPIO_PORT(CC, 0x5400, 4, 5),
|
|
};
|
|
|
|
static const struct tegra_gpio_soc tegra186_main_soc = {
|
|
.num_ports = ARRAY_SIZE(tegra186_main_ports),
|
|
.ports = tegra186_main_ports,
|
|
.name = "tegra186-gpio",
|
|
};
|
|
|
|
#define TEGRA186_AON_GPIO_PORT(port, base, count, controller) \
|
|
[TEGRA186_AON_GPIO_PORT_##port] = { \
|
|
.name = #port, \
|
|
.offset = base, \
|
|
.pins = count, \
|
|
.irq = controller, \
|
|
}
|
|
|
|
static const struct tegra_gpio_port tegra186_aon_ports[] = {
|
|
TEGRA186_AON_GPIO_PORT( S, 0x0200, 5, 0),
|
|
TEGRA186_AON_GPIO_PORT( U, 0x0400, 6, 0),
|
|
TEGRA186_AON_GPIO_PORT( V, 0x0800, 8, 0),
|
|
TEGRA186_AON_GPIO_PORT( W, 0x0a00, 8, 0),
|
|
TEGRA186_AON_GPIO_PORT( Z, 0x0e00, 4, 0),
|
|
TEGRA186_AON_GPIO_PORT(AA, 0x0c00, 8, 0),
|
|
TEGRA186_AON_GPIO_PORT(EE, 0x0600, 3, 0),
|
|
TEGRA186_AON_GPIO_PORT(FF, 0x0000, 5, 0),
|
|
};
|
|
|
|
static const struct tegra_gpio_soc tegra186_aon_soc = {
|
|
.num_ports = ARRAY_SIZE(tegra186_aon_ports),
|
|
.ports = tegra186_aon_ports,
|
|
.name = "tegra186-gpio-aon",
|
|
};
|
|
|
|
#define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller) \
|
|
[TEGRA194_MAIN_GPIO_PORT_##port] = { \
|
|
.name = #port, \
|
|
.offset = base, \
|
|
.pins = count, \
|
|
.irq = controller, \
|
|
}
|
|
|
|
static const struct tegra_gpio_port tegra194_main_ports[] = {
|
|
TEGRA194_MAIN_GPIO_PORT( A, 0x1400, 8, 1),
|
|
TEGRA194_MAIN_GPIO_PORT( B, 0x4e00, 2, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( D, 0x4800, 4, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( E, 0x4a00, 8, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( F, 0x4c00, 6, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( G, 0x4000, 8, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( H, 0x4200, 8, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( I, 0x4400, 5, 4),
|
|
TEGRA194_MAIN_GPIO_PORT( J, 0x5200, 6, 5),
|
|
TEGRA194_MAIN_GPIO_PORT( K, 0x3000, 8, 3),
|
|
TEGRA194_MAIN_GPIO_PORT( L, 0x3200, 4, 3),
|
|
TEGRA194_MAIN_GPIO_PORT( M, 0x2600, 8, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( N, 0x2800, 3, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( O, 0x5000, 6, 5),
|
|
TEGRA194_MAIN_GPIO_PORT( P, 0x2a00, 8, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( Q, 0x2c00, 8, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( R, 0x2e00, 6, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( S, 0x3600, 8, 3),
|
|
TEGRA194_MAIN_GPIO_PORT( T, 0x3800, 8, 3),
|
|
TEGRA194_MAIN_GPIO_PORT( U, 0x3a00, 1, 3),
|
|
TEGRA194_MAIN_GPIO_PORT( V, 0x1000, 8, 1),
|
|
TEGRA194_MAIN_GPIO_PORT( W, 0x1200, 2, 1),
|
|
TEGRA194_MAIN_GPIO_PORT( X, 0x2000, 8, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( Y, 0x2200, 8, 2),
|
|
TEGRA194_MAIN_GPIO_PORT( Z, 0x2400, 8, 2),
|
|
TEGRA194_MAIN_GPIO_PORT(FF, 0x3400, 2, 3),
|
|
TEGRA194_MAIN_GPIO_PORT(GG, 0x0000, 2, 0)
|
|
};
|
|
|
|
static const struct tegra_gpio_soc tegra194_main_soc = {
|
|
.num_ports = ARRAY_SIZE(tegra194_main_ports),
|
|
.ports = tegra194_main_ports,
|
|
.name = "tegra194-gpio",
|
|
};
|
|
|
|
#define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \
|
|
[TEGRA194_AON_GPIO_PORT_##port] = { \
|
|
.name = #port, \
|
|
.offset = base, \
|
|
.pins = count, \
|
|
.irq = controller, \
|
|
}
|
|
|
|
static const struct tegra_gpio_port tegra194_aon_ports[] = {
|
|
TEGRA194_AON_GPIO_PORT(AA, 0x0600, 8, 0),
|
|
TEGRA194_AON_GPIO_PORT(BB, 0x0800, 4, 0),
|
|
TEGRA194_AON_GPIO_PORT(CC, 0x0200, 8, 0),
|
|
TEGRA194_AON_GPIO_PORT(DD, 0x0400, 3, 0),
|
|
TEGRA194_AON_GPIO_PORT(EE, 0x0000, 7, 0)
|
|
};
|
|
|
|
static const struct tegra_gpio_soc tegra194_aon_soc = {
|
|
.num_ports = ARRAY_SIZE(tegra194_aon_ports),
|
|
.ports = tegra194_aon_ports,
|
|
.name = "tegra194-gpio-aon",
|
|
};
|
|
|
|
static const struct of_device_id tegra186_gpio_of_match[] = {
|
|
{
|
|
.compatible = "nvidia,tegra186-gpio",
|
|
.data = &tegra186_main_soc
|
|
}, {
|
|
.compatible = "nvidia,tegra186-gpio-aon",
|
|
.data = &tegra186_aon_soc
|
|
}, {
|
|
.compatible = "nvidia,tegra194-gpio",
|
|
.data = &tegra194_main_soc
|
|
}, {
|
|
.compatible = "nvidia,tegra194-gpio-aon",
|
|
.data = &tegra194_aon_soc
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct platform_driver tegra186_gpio_driver = {
|
|
.driver = {
|
|
.name = "tegra186-gpio",
|
|
.of_match_table = tegra186_gpio_of_match,
|
|
},
|
|
.probe = tegra186_gpio_probe,
|
|
.remove = tegra186_gpio_remove,
|
|
};
|
|
module_platform_driver(tegra186_gpio_driver);
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
|
|
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
|
|
MODULE_LICENSE("GPL v2");
|