567 lines
14 KiB
C
567 lines
14 KiB
C
/*
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* Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/mbus.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include "pcie-iproc.h"
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#define EP_PERST_SOURCE_SELECT_SHIFT 2
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#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
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#define EP_MODE_SURVIVE_PERST_SHIFT 1
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#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
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#define RC_PCIE_RST_OUTPUT_SHIFT 0
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#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
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#define PAXC_RESET_MASK 0x7f
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#define CFG_IND_ADDR_MASK 0x00001ffc
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#define CFG_ADDR_BUS_NUM_SHIFT 20
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#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
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#define CFG_ADDR_DEV_NUM_SHIFT 15
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#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
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#define CFG_ADDR_FUNC_NUM_SHIFT 12
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#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
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#define CFG_ADDR_REG_NUM_SHIFT 2
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#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
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#define CFG_ADDR_CFG_TYPE_SHIFT 0
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#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
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#define SYS_RC_INTX_MASK 0xf
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#define PCIE_PHYLINKUP_SHIFT 3
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#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
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#define PCIE_DL_ACTIVE_SHIFT 2
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#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
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#define OARR_VALID_SHIFT 0
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#define OARR_VALID BIT(OARR_VALID_SHIFT)
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#define OARR_SIZE_CFG_SHIFT 1
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#define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT)
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#define MAX_NUM_OB_WINDOWS 2
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#define IPROC_PCIE_REG_INVALID 0xffff
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enum iproc_pcie_reg {
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IPROC_PCIE_CLK_CTRL = 0,
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IPROC_PCIE_CFG_IND_ADDR,
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IPROC_PCIE_CFG_IND_DATA,
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IPROC_PCIE_CFG_ADDR,
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IPROC_PCIE_CFG_DATA,
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IPROC_PCIE_INTX_EN,
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IPROC_PCIE_OARR_LO,
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IPROC_PCIE_OARR_HI,
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IPROC_PCIE_OMAP_LO,
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IPROC_PCIE_OMAP_HI,
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IPROC_PCIE_LINK_STATUS,
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};
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/* iProc PCIe PAXB registers */
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static const u16 iproc_pcie_reg_paxb[] = {
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[IPROC_PCIE_CLK_CTRL] = 0x000,
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[IPROC_PCIE_CFG_IND_ADDR] = 0x120,
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[IPROC_PCIE_CFG_IND_DATA] = 0x124,
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[IPROC_PCIE_CFG_ADDR] = 0x1f8,
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[IPROC_PCIE_CFG_DATA] = 0x1fc,
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[IPROC_PCIE_INTX_EN] = 0x330,
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[IPROC_PCIE_OARR_LO] = 0xd20,
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[IPROC_PCIE_OARR_HI] = 0xd24,
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[IPROC_PCIE_OMAP_LO] = 0xd40,
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[IPROC_PCIE_OMAP_HI] = 0xd44,
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[IPROC_PCIE_LINK_STATUS] = 0xf0c,
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};
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/* iProc PCIe PAXC v1 registers */
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static const u16 iproc_pcie_reg_paxc[] = {
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[IPROC_PCIE_CLK_CTRL] = 0x000,
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[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
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[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
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[IPROC_PCIE_CFG_ADDR] = 0x1f8,
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[IPROC_PCIE_CFG_DATA] = 0x1fc,
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[IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID,
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[IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID,
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[IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID,
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[IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID,
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[IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID,
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[IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID,
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};
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static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
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{
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struct iproc_pcie *pcie;
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#ifdef CONFIG_ARM
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struct pci_sys_data *sys = bus->sysdata;
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pcie = sys->private_data;
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#else
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pcie = bus->sysdata;
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#endif
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return pcie;
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}
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static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
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{
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return !!(reg_offset == IPROC_PCIE_REG_INVALID);
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}
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static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
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enum iproc_pcie_reg reg)
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{
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return pcie->reg_offsets[reg];
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}
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static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
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enum iproc_pcie_reg reg)
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{
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u16 offset = iproc_pcie_reg_offset(pcie, reg);
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if (iproc_pcie_reg_is_invalid(offset))
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return 0;
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return readl(pcie->base + offset);
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}
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static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
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enum iproc_pcie_reg reg, u32 val)
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{
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u16 offset = iproc_pcie_reg_offset(pcie, reg);
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if (iproc_pcie_reg_is_invalid(offset))
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return;
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writel(val, pcie->base + offset);
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}
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static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
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enum iproc_pcie_reg reg,
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unsigned window, u32 val)
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{
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u16 offset = iproc_pcie_reg_offset(pcie, reg);
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if (iproc_pcie_reg_is_invalid(offset))
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return;
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writel(val, pcie->base + offset + (window * 8));
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}
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/**
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* Note access to the configuration registers are protected at the higher layer
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* by 'pci_lock' in drivers/pci/access.c
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*/
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static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
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unsigned int devfn,
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int where)
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{
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struct iproc_pcie *pcie = iproc_data(bus);
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unsigned slot = PCI_SLOT(devfn);
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unsigned fn = PCI_FUNC(devfn);
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unsigned busno = bus->number;
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u32 val;
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u16 offset;
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/* root complex access */
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if (busno == 0) {
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if (slot > 0 || fn > 0)
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return NULL;
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
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where & CFG_IND_ADDR_MASK);
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offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
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if (iproc_pcie_reg_is_invalid(offset))
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return NULL;
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else
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return (pcie->base + offset);
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}
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/*
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* PAXC is connected to an internally emulated EP within the SoC. It
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* allows only one device.
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*/
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if (pcie->type == IPROC_PCIE_PAXC)
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if (slot > 0)
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return NULL;
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/* EP device access */
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val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
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(slot << CFG_ADDR_DEV_NUM_SHIFT) |
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(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
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(where & CFG_ADDR_REG_NUM_MASK) |
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(1 & CFG_ADDR_CFG_TYPE_MASK);
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
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offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
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if (iproc_pcie_reg_is_invalid(offset))
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return NULL;
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else
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return (pcie->base + offset);
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}
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static struct pci_ops iproc_pcie_ops = {
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.map_bus = iproc_pcie_map_cfg_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static void iproc_pcie_reset(struct iproc_pcie *pcie)
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{
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u32 val;
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if (pcie->type == IPROC_PCIE_PAXC) {
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val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
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val &= ~PAXC_RESET_MASK;
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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udelay(100);
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val |= PAXC_RESET_MASK;
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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udelay(100);
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return;
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}
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/*
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* Select perst_b signal as reset source. Put the device into reset,
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* and then bring it out of reset
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*/
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val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
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val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
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~RC_PCIE_RST_OUTPUT;
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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udelay(250);
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val |= RC_PCIE_RST_OUTPUT;
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iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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msleep(100);
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}
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static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
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{
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u8 hdr_type;
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u32 link_ctrl, class, val;
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u16 pos, link_status;
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bool link_is_active = false;
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/*
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* PAXC connects to emulated endpoint devices directly and does not
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* have a Serdes. Therefore skip the link detection logic here.
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*/
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if (pcie->type == IPROC_PCIE_PAXC)
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return 0;
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val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
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if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
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dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
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return -ENODEV;
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}
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/* make sure we are not in EP mode */
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pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
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if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
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dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
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return -EFAULT;
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}
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/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
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#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
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#define PCI_CLASS_BRIDGE_MASK 0xffff00
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#define PCI_CLASS_BRIDGE_SHIFT 8
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pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
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class &= ~PCI_CLASS_BRIDGE_MASK;
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class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
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pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
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/* check link status to see if link is active */
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pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
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if (link_status & PCI_EXP_LNKSTA_NLW)
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link_is_active = true;
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if (!link_is_active) {
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/* try GEN 1 link speed */
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#define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
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#define PCI_TARGET_LINK_SPEED_MASK 0xf
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#define PCI_TARGET_LINK_SPEED_GEN2 0x2
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#define PCI_TARGET_LINK_SPEED_GEN1 0x1
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pci_bus_read_config_dword(bus, 0,
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PCI_LINK_STATUS_CTRL_2_OFFSET,
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&link_ctrl);
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if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
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PCI_TARGET_LINK_SPEED_GEN2) {
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link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
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link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
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pci_bus_write_config_dword(bus, 0,
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PCI_LINK_STATUS_CTRL_2_OFFSET,
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link_ctrl);
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msleep(100);
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pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
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&link_status);
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if (link_status & PCI_EXP_LNKSTA_NLW)
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link_is_active = true;
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}
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}
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dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
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return link_is_active ? 0 : -ENODEV;
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}
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static void iproc_pcie_enable(struct iproc_pcie *pcie)
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{
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iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
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}
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/**
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* Some iProc SoCs require the SW to configure the outbound address mapping
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*
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* Outbound address translation:
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*
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* iproc_pcie_address = axi_address - axi_offset
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* OARR = iproc_pcie_address
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* OMAP = pci_addr
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*
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* axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
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*/
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static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
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u64 pci_addr, resource_size_t size)
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{
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struct iproc_pcie_ob *ob = &pcie->ob;
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unsigned i;
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u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
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u64 remainder;
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if (size > max_size) {
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dev_err(pcie->dev,
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"res size %pap exceeds max supported size 0x%llx\n",
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&size, max_size);
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return -EINVAL;
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}
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div64_u64_rem(size, ob->window_size, &remainder);
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if (remainder) {
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dev_err(pcie->dev,
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"res size %pap needs to be multiple of window size %pap\n",
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&size, &ob->window_size);
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return -EINVAL;
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}
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if (axi_addr < ob->axi_offset) {
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dev_err(pcie->dev,
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"axi address %pap less than offset %pap\n",
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&axi_addr, &ob->axi_offset);
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return -EINVAL;
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}
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/*
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* Translate the AXI address to the internal address used by the iProc
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* PCIe core before programming the OARR
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*/
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axi_addr -= ob->axi_offset;
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for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
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iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
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lower_32_bits(axi_addr) | OARR_VALID |
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(ob->set_oarr_size ? 1 : 0));
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iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
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upper_32_bits(axi_addr));
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iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
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lower_32_bits(pci_addr));
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iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
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upper_32_bits(pci_addr));
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size -= ob->window_size;
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if (size == 0)
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break;
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axi_addr += ob->window_size;
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pci_addr += ob->window_size;
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}
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return 0;
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}
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static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
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struct list_head *resources)
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{
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struct resource_entry *window;
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int ret;
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resource_list_for_each_entry(window, resources) {
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struct resource *res = window->res;
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u64 res_type = resource_type(res);
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switch (res_type) {
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case IORESOURCE_IO:
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case IORESOURCE_BUS:
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break;
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case IORESOURCE_MEM:
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ret = iproc_pcie_setup_ob(pcie, res->start,
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res->start - window->offset,
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resource_size(res));
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if (ret)
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return ret;
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break;
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default:
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dev_err(pcie->dev, "invalid resource %pR\n", res);
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return -EINVAL;
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}
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}
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return 0;
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}
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static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
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{
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struct device_node *msi_node;
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msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
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if (!msi_node)
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return -ENODEV;
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/*
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* If another MSI controller is being used, the call below should fail
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* but that is okay
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*/
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return iproc_msi_init(pcie, msi_node);
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}
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static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
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{
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iproc_msi_exit(pcie);
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}
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int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
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{
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int ret;
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void *sysdata;
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struct pci_bus *bus;
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if (!pcie || !pcie->dev || !pcie->base)
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return -EINVAL;
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ret = devm_request_pci_bus_resources(pcie->dev, res);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = phy_init(pcie->phy);
|
|
if (ret) {
|
|
dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = phy_power_on(pcie->phy);
|
|
if (ret) {
|
|
dev_err(pcie->dev, "unable to power on PCIe PHY\n");
|
|
goto err_exit_phy;
|
|
}
|
|
|
|
switch (pcie->type) {
|
|
case IPROC_PCIE_PAXB:
|
|
pcie->reg_offsets = iproc_pcie_reg_paxb;
|
|
break;
|
|
case IPROC_PCIE_PAXC:
|
|
pcie->reg_offsets = iproc_pcie_reg_paxc;
|
|
break;
|
|
default:
|
|
dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
|
|
ret = -EINVAL;
|
|
goto err_power_off_phy;
|
|
}
|
|
|
|
iproc_pcie_reset(pcie);
|
|
|
|
if (pcie->need_ob_cfg) {
|
|
ret = iproc_pcie_map_ranges(pcie, res);
|
|
if (ret) {
|
|
dev_err(pcie->dev, "map failed\n");
|
|
goto err_power_off_phy;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_ARM
|
|
pcie->sysdata.private_data = pcie;
|
|
sysdata = &pcie->sysdata;
|
|
#else
|
|
sysdata = pcie;
|
|
#endif
|
|
|
|
bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
|
|
if (!bus) {
|
|
dev_err(pcie->dev, "unable to create PCI root bus\n");
|
|
ret = -ENOMEM;
|
|
goto err_power_off_phy;
|
|
}
|
|
pcie->root_bus = bus;
|
|
|
|
ret = iproc_pcie_check_link(pcie, bus);
|
|
if (ret) {
|
|
dev_err(pcie->dev, "no PCIe EP device detected\n");
|
|
goto err_rm_root_bus;
|
|
}
|
|
|
|
iproc_pcie_enable(pcie);
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI))
|
|
if (iproc_pcie_msi_enable(pcie))
|
|
dev_info(pcie->dev, "not using iProc MSI\n");
|
|
|
|
pci_scan_child_bus(bus);
|
|
pci_assign_unassigned_bus_resources(bus);
|
|
pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
|
|
pci_bus_add_devices(bus);
|
|
|
|
return 0;
|
|
|
|
err_rm_root_bus:
|
|
pci_stop_root_bus(bus);
|
|
pci_remove_root_bus(bus);
|
|
|
|
err_power_off_phy:
|
|
phy_power_off(pcie->phy);
|
|
err_exit_phy:
|
|
phy_exit(pcie->phy);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(iproc_pcie_setup);
|
|
|
|
int iproc_pcie_remove(struct iproc_pcie *pcie)
|
|
{
|
|
pci_stop_root_bus(pcie->root_bus);
|
|
pci_remove_root_bus(pcie->root_bus);
|
|
|
|
iproc_pcie_msi_disable(pcie);
|
|
|
|
phy_power_off(pcie->phy);
|
|
phy_exit(pcie->phy);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(iproc_pcie_remove);
|
|
|
|
MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
|
|
MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
|
|
MODULE_LICENSE("GPL v2");
|