591 lines
14 KiB
C
591 lines
14 KiB
C
/*
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* Copyright Altera Corporation (C) 2013-2015. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define RP_TX_REG0 0x2000
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#define RP_TX_REG1 0x2004
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#define RP_TX_CNTRL 0x2008
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#define RP_TX_EOP 0x2
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#define RP_TX_SOP 0x1
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#define RP_RXCPL_STATUS 0x2010
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#define RP_RXCPL_EOP 0x2
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#define RP_RXCPL_SOP 0x1
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#define RP_RXCPL_REG0 0x2014
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#define RP_RXCPL_REG1 0x2018
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#define P2A_INT_STATUS 0x3060
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#define P2A_INT_STS_ALL 0xf
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#define P2A_INT_ENABLE 0x3070
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#define P2A_INT_ENA_ALL 0xf
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#define RP_LTSSM 0x3c64
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#define RP_LTSSM_MASK 0x1f
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#define LTSSM_L0 0xf
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/* TLP configuration type 0 and 1 */
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#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
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#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
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#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
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#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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#define TLP_PAYLOAD_SIZE 0x01
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#define TLP_READ_TAG 0x1d
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#define TLP_WRITE_TAG 0x10
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#define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
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#define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
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#define TLP_CFG_DW2(bus, devfn, offset) \
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(((bus) << 24) | ((devfn) << 16) | (offset))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
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#define TLP_HDR_SIZE 3
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#define TLP_LOOP 500
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#define RP_DEVFN 0
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#define LINK_UP_TIMEOUT 5000
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#define INTX_NUM 4
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#define DWORD_MASK 3
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struct altera_pcie {
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struct platform_device *pdev;
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void __iomem *cra_base;
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int irq;
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u8 root_bus_nr;
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struct irq_domain *irq_domain;
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struct resource bus_range;
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struct list_head resources;
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};
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struct tlp_rp_regpair_t {
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u32 ctrl;
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u32 reg0;
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u32 reg1;
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};
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static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
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const u32 reg)
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{
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writel_relaxed(value, pcie->cra_base + reg);
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}
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static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
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{
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return readl_relaxed(pcie->cra_base + reg);
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}
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static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
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{
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return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
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}
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static void altera_pcie_retrain(struct pci_dev *dev)
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{
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u16 linkcap, linkstat;
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struct altera_pcie *pcie = dev->bus->sysdata;
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int timeout = 0;
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if (!altera_pcie_link_is_up(pcie))
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return;
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/*
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* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
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* current speed is 2.5 GB/s.
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*/
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pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
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if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
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return;
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pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
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if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
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pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_RL);
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while (!altera_pcie_link_is_up(pcie)) {
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timeout++;
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if (timeout > LINK_UP_TIMEOUT)
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break;
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udelay(5);
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}
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}
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}
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DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
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/*
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* Altera PCIe port uses BAR0 of RC's configuration space as the translation
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* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
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* using these registers, so it can be reached by DMA from EP devices.
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* This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
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* from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
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* should be hidden during enumeration to avoid the sizing and resource
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* allocation by PCIe core.
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*/
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static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
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int offset)
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{
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if (pci_is_root_bus(bus) && (devfn == 0) &&
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(offset == PCI_BASE_ADDRESS_0))
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return true;
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return false;
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}
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static void tlp_write_tx(struct altera_pcie *pcie,
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struct tlp_rp_regpair_t *tlp_rp_regdata)
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{
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cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
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cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
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cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
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}
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static bool altera_pcie_valid_config(struct altera_pcie *pcie,
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struct pci_bus *bus, int dev)
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{
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/* If there is no link, then there is no device */
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if (bus->number != pcie->root_bus_nr) {
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if (!altera_pcie_link_is_up(pcie))
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return false;
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}
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/* access only one slot on each root port */
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if (bus->number == pcie->root_bus_nr && dev > 0)
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return false;
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/*
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* Do not read more than one device on the bus directly attached
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* to root port, root port can only attach to one downstream port.
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*/
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if (bus->primary == pcie->root_bus_nr && dev > 0)
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return false;
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return true;
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}
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static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
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{
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int i;
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bool sop = 0;
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u32 ctrl;
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u32 reg0, reg1;
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u32 comp_status = 1;
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/*
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* Minimum 2 loops to read TLP headers and 1 loop to read data
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* payload.
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*/
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for (i = 0; i < TLP_LOOP; i++) {
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ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
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if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
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reg0 = cra_readl(pcie, RP_RXCPL_REG0);
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reg1 = cra_readl(pcie, RP_RXCPL_REG1);
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if (ctrl & RP_RXCPL_SOP) {
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sop = true;
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comp_status = TLP_COMP_STATUS(reg1);
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}
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if (ctrl & RP_RXCPL_EOP) {
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if (comp_status)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (value)
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*value = reg0;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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udelay(5);
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}
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
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u32 data, bool align)
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{
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struct tlp_rp_regpair_t tlp_rp_regdata;
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tlp_rp_regdata.reg0 = headers[0];
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tlp_rp_regdata.reg1 = headers[1];
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tlp_rp_regdata.ctrl = RP_TX_SOP;
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tlp_write_tx(pcie, &tlp_rp_regdata);
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if (align) {
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tlp_rp_regdata.reg0 = headers[2];
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tlp_rp_regdata.reg1 = 0;
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tlp_rp_regdata.ctrl = 0;
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tlp_write_tx(pcie, &tlp_rp_regdata);
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tlp_rp_regdata.reg0 = data;
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tlp_rp_regdata.reg1 = 0;
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} else {
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tlp_rp_regdata.reg0 = headers[2];
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tlp_rp_regdata.reg1 = data;
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}
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tlp_rp_regdata.ctrl = RP_TX_EOP;
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tlp_write_tx(pcie, &tlp_rp_regdata);
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}
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static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
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int where, u8 byte_en, u32 *value)
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{
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u32 headers[TLP_HDR_SIZE];
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if (bus == pcie->root_bus_nr)
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
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else
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
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TLP_READ_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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tlp_write_packet(pcie, headers, 0, false);
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return tlp_read_packet(pcie, value);
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}
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static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
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int where, u8 byte_en, u32 value)
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{
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u32 headers[TLP_HDR_SIZE];
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int ret;
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if (bus == pcie->root_bus_nr)
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
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else
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headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
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headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
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TLP_WRITE_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(bus, devfn, where);
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/* check alignment to Qword */
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if ((where & 0x7) == 0)
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tlp_write_packet(pcie, headers, value, true);
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else
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tlp_write_packet(pcie, headers, value, false);
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ret = tlp_read_packet(pcie, NULL);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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/*
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* Monitor changes to PCI_PRIMARY_BUS register on root port
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* and update local copy of root bus number accordingly.
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*/
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if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
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pcie->root_bus_nr = (u8)(value);
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return PCIBIOS_SUCCESSFUL;
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}
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static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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struct altera_pcie *pcie = bus->sysdata;
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int ret;
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u32 data;
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u8 byte_en;
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if (altera_pcie_hide_rc_bar(bus, devfn, where))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
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*value = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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switch (size) {
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case 1:
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byte_en = 1 << (where & 3);
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break;
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case 2:
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byte_en = 3 << (where & 3);
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break;
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default:
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byte_en = 0xf;
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break;
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}
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ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
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(where & ~DWORD_MASK), byte_en, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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switch (size) {
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case 1:
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*value = (data >> (8 * (where & 0x3))) & 0xff;
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break;
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case 2:
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*value = (data >> (8 * (where & 0x2))) & 0xffff;
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break;
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default:
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*value = data;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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struct altera_pcie *pcie = bus->sysdata;
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u32 data32;
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u32 shift = 8 * (where & 3);
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u8 byte_en;
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if (altera_pcie_hide_rc_bar(bus, devfn, where))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1:
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data32 = (value & 0xff) << shift;
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byte_en = 1 << (where & 3);
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break;
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case 2:
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data32 = (value & 0xffff) << shift;
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byte_en = 3 << (where & 3);
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break;
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default:
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data32 = value;
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byte_en = 0xf;
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break;
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}
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return tlp_cfg_dword_write(pcie, bus->number, devfn,
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(where & ~DWORD_MASK), byte_en, data32);
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}
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static struct pci_ops altera_pcie_ops = {
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.read = altera_pcie_cfg_read,
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.write = altera_pcie_cfg_write,
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};
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static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = altera_pcie_intx_map,
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};
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static void altera_pcie_isr(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct altera_pcie *pcie;
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unsigned long status;
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u32 bit;
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u32 virq;
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chained_irq_enter(chip, desc);
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pcie = irq_desc_get_handler_data(desc);
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while ((status = cra_readl(pcie, P2A_INT_STATUS)
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& P2A_INT_STS_ALL) != 0) {
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for_each_set_bit(bit, &status, INTX_NUM) {
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/* clear interrupts */
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cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
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virq = irq_find_mapping(pcie->irq_domain, bit + 1);
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if (virq)
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generic_handle_irq(virq);
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else
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dev_err(&pcie->pdev->dev,
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"unexpected IRQ, INT%d\n", bit);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
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{
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int err, res_valid = 0;
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struct device *dev = &pcie->pdev->dev;
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struct device_node *np = dev->of_node;
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struct resource_entry *win;
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err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
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NULL);
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if (err)
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return err;
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err = devm_request_pci_bus_resources(dev, &pcie->resources);
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if (err)
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goto out_release_res;
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resource_list_for_each_entry(win, &pcie->resources) {
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struct resource *res = win->res;
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if (resource_type(res) == IORESOURCE_MEM)
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res_valid |= !(res->flags & IORESOURCE_PREFETCH);
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}
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if (res_valid)
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return 0;
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dev_err(dev, "non-prefetchable memory resource required\n");
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err = -EINVAL;
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out_release_res:
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pci_free_resource_list(&pcie->resources);
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return err;
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}
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static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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struct device_node *node = dev->of_node;
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/* Setup INTx */
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pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
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&intx_domain_ops, pcie);
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if (!pcie->irq_domain) {
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dev_err(dev, "Failed to get a INTx IRQ domain\n");
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return -ENOMEM;
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}
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return 0;
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}
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static int altera_pcie_parse_dt(struct altera_pcie *pcie)
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{
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struct resource *cra;
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struct platform_device *pdev = pcie->pdev;
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cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
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if (!cra) {
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dev_err(&pdev->dev, "no Cra memory resource defined\n");
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return -ENODEV;
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}
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pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
|
|
if (IS_ERR(pcie->cra_base)) {
|
|
dev_err(&pdev->dev, "failed to map cra memory\n");
|
|
return PTR_ERR(pcie->cra_base);
|
|
}
|
|
|
|
/* setup IRQ */
|
|
pcie->irq = platform_get_irq(pdev, 0);
|
|
if (pcie->irq <= 0) {
|
|
dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int altera_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct altera_pcie *pcie;
|
|
struct pci_bus *bus;
|
|
struct pci_bus *child;
|
|
int ret;
|
|
|
|
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
|
|
if (!pcie)
|
|
return -ENOMEM;
|
|
|
|
pcie->pdev = pdev;
|
|
|
|
ret = altera_pcie_parse_dt(pcie);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Parsing DT failed\n");
|
|
return ret;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&pcie->resources);
|
|
|
|
ret = altera_pcie_parse_request_of_pci_ranges(pcie);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed add resources\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = altera_pcie_init_irq_domain(pcie);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
|
|
return ret;
|
|
}
|
|
|
|
/* clear all interrupts */
|
|
cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
|
|
/* enable all interrupts */
|
|
cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
|
|
|
|
bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
|
|
pcie, &pcie->resources);
|
|
if (!bus)
|
|
return -ENOMEM;
|
|
|
|
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
|
pci_assign_unassigned_bus_resources(bus);
|
|
|
|
/* Configure PCI Express setting. */
|
|
list_for_each_entry(child, &bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
|
|
pci_bus_add_devices(bus);
|
|
|
|
platform_set_drvdata(pdev, pcie);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id altera_pcie_of_match[] = {
|
|
{ .compatible = "altr,pcie-root-port-1.0", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
|
|
|
|
static struct platform_driver altera_pcie_driver = {
|
|
.probe = altera_pcie_probe,
|
|
.driver = {
|
|
.name = "altera-pcie",
|
|
.of_match_table = altera_pcie_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
|
|
static int altera_pcie_init(void)
|
|
{
|
|
return platform_driver_register(&altera_pcie_driver);
|
|
}
|
|
module_init(altera_pcie_init);
|
|
|
|
MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
|
|
MODULE_DESCRIPTION("Altera PCIe host controller driver");
|
|
MODULE_LICENSE("GPL v2");
|