59b5809655
There are two implemented bits in the PPIN_CTL MSR:
Bit 0: LockOut (R/WO)
Set 1 to prevent further writes to MSR_PPIN_CTL.
Bit 1: Enable_PPIN (R/W)
If 1, enables MSR_PPIN to be accessible using RDMSR.
If 0, an attempt to read MSR_PPIN will cause #GP.
So there are four defined values:
0: PPIN is disabled, PPIN_CTL may be updated
1: PPIN is disabled. PPIN_CTL is locked against updates
2: PPIN is enabled. PPIN_CTL may be updated
3: PPIN is enabled. PPIN_CTL is locked against updates
Code would only enable the X86_FEATURE_INTEL_PPIN feature for case "2".
When it should have done so for both case "2" and case "3".
Fix the final test to just check for the enable bit. Also fix some of
the other comments in this function.
Fixes:
|
||
|---|---|---|
| .. | ||
| Makefile | ||
| amd.c | ||
| apei.c | ||
| core.c | ||
| dev-mcelog.c | ||
| genpool.c | ||
| inject.c | ||
| intel.c | ||
| internal.h | ||
| p5.c | ||
| severity.c | ||
| therm_throt.c | ||
| threshold.c | ||
| winchip.c | ||