182 lines
6.2 KiB
C
182 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/include/asm-arm/arch-pxa/balloon3.h
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*
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* Authors: Nick Bane and Wookey
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* Created: Oct, 2005
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* Copyright: Toby Churchill Ltd
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* Cribbed from mainstone.c, by Nicholas Pitre
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*/
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#ifndef ASM_ARCH_BALLOON3_H
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#define ASM_ARCH_BALLOON3_H
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#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
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enum balloon3_features {
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BALLOON3_FEATURE_OHCI,
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BALLOON3_FEATURE_MMC,
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BALLOON3_FEATURE_CF,
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BALLOON3_FEATURE_AUDIO,
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BALLOON3_FEATURE_TOPPOLY,
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};
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#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS
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#define BALLOON3_FPGA_VIRT IOMEM(0xf1000000) /* as per balloon2 */
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#define BALLOON3_FPGA_LENGTH 0x01000000
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#define BALLOON3_FPGA_SETnCLR (0x1000)
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/* FPGA / CPLD registers for CF socket */
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#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
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#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
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/* FPGA / CPLD version register */
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#define BALLOON3_FPGA_VER (BALLOON3_FPGA_VIRT + 0x00e0001c)
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/* FPGA / CPLD registers for NAND flash */
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#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000)
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#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
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#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
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#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
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#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
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/* fpga/cpld interrupt control register */
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#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C)
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#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c)
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#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000)
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#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004)
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#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c)
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/* CF Status Register bits (read-only) bits */
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#define BALLOON3_CF_nIRQ (1 << 0)
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#define BALLOON3_CF_nSTSCHG_BVD1 (1 << 1)
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/* CF Control Set Register bits / CF Control Clear Register bits (write-only) */
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#define BALLOON3_CF_RESET (1 << 0)
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#define BALLOON3_CF_ENABLE (1 << 1)
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#define BALLOON3_CF_ADD_ENABLE (1 << 2)
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/* CF Interrupt sources */
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#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
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#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
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/* NAND Control register */
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#define BALLOON3_NAND_CONTROL_FLWP (1 << 7)
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#define BALLOON3_NAND_CONTROL_FLSE (1 << 6)
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#define BALLOON3_NAND_CONTROL_FLCE3 (1 << 5)
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#define BALLOON3_NAND_CONTROL_FLCE2 (1 << 4)
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#define BALLOON3_NAND_CONTROL_FLCE1 (1 << 3)
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#define BALLOON3_NAND_CONTROL_FLCE0 (1 << 2)
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#define BALLOON3_NAND_CONTROL_FLALE (1 << 1)
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#define BALLOON3_NAND_CONTROL_FLCLE (1 << 0)
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/* NAND Status register */
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#define BALLOON3_NAND_STAT_RNB (1 << 0)
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/* NAND Control2 register */
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#define BALLOON3_NAND_CONTROL2_16BIT (1 << 0)
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/* GPIOs for irqs */
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#define BALLOON3_GPIO_AUX_NIRQ (94)
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#define BALLOON3_GPIO_CODEC_IRQ (95)
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/* Timer and Idle LED locations */
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#define BALLOON3_GPIO_LED_NAND (9)
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#define BALLOON3_GPIO_LED_IDLE (10)
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/* backlight control */
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#define BALLOON3_GPIO_RUN_BACKLIGHT (99)
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#define BALLOON3_GPIO_S0_CD (105)
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/* NAND */
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#define BALLOON3_GPIO_RUN_NAND (102)
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/* PCF8574A Leds */
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#define BALLOON3_PCF_GPIO_BASE 160
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#define BALLOON3_PCF_GPIO_LED0 (BALLOON3_PCF_GPIO_BASE + 0)
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#define BALLOON3_PCF_GPIO_LED1 (BALLOON3_PCF_GPIO_BASE + 1)
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#define BALLOON3_PCF_GPIO_LED2 (BALLOON3_PCF_GPIO_BASE + 2)
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#define BALLOON3_PCF_GPIO_LED3 (BALLOON3_PCF_GPIO_BASE + 3)
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#define BALLOON3_PCF_GPIO_LED4 (BALLOON3_PCF_GPIO_BASE + 4)
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#define BALLOON3_PCF_GPIO_LED5 (BALLOON3_PCF_GPIO_BASE + 5)
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#define BALLOON3_PCF_GPIO_LED6 (BALLOON3_PCF_GPIO_BASE + 6)
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#define BALLOON3_PCF_GPIO_LED7 (BALLOON3_PCF_GPIO_BASE + 7)
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/* FPGA Interrupt Mask/Acknowledge Register */
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#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */
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#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */
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/* CPLD (and FPGA) interface definitions */
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#define CPLD_LCD0_DATA_SET 0x00
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#define CPLD_LCD0_DATA_CLR 0x10
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#define CPLD_LCD0_COMMAND_SET 0x01
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#define CPLD_LCD0_COMMAND_CLR 0x11
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#define CPLD_LCD1_DATA_SET 0x02
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#define CPLD_LCD1_DATA_CLR 0x12
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#define CPLD_LCD1_COMMAND_SET 0x03
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#define CPLD_LCD1_COMMAND_CLR 0x13
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#define CPLD_MISC_SET 0x07
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#define CPLD_MISC_CLR 0x17
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#define CPLD_MISC_LOON_NRESET_BIT 0
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#define CPLD_MISC_LOON_UNSUSP_BIT 1
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#define CPLD_MISC_RUN_5V_BIT 2
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#define CPLD_MISC_CHG_D0_BIT 3
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#define CPLD_MISC_CHG_D1_BIT 4
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#define CPLD_MISC_DAC_NCS_BIT 5
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#define CPLD_LCD_SET 0x08
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#define CPLD_LCD_CLR 0x18
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#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0
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#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1
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#define CPLD_LCD_LED_RED_BIT 4
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#define CPLD_LCD_LED_GREEN_BIT 5
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#define CPLD_LCD_NRESET_BIT 7
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#define CPLD_LCD_RO_SET 0x09
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#define CPLD_LCD_RO_CLR 0x19
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#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0
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#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1
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#define CPLD_SERIAL_SET 0x0a
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#define CPLD_SERIAL_CLR 0x1a
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#define CPLD_SERIAL_GSM_RI_BIT 0
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#define CPLD_SERIAL_GSM_CTS_BIT 1
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#define CPLD_SERIAL_GSM_DTR_BIT 2
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#define CPLD_SERIAL_LPR_CTS_BIT 3
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#define CPLD_SERIAL_TC232_CTS_BIT 4
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#define CPLD_SERIAL_TC232_DSR_BIT 5
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#define CPLD_SROUTING_SET 0x0b
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#define CPLD_SROUTING_CLR 0x1b
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#define CPLD_SROUTING_MSP430_LPR 0
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#define CPLD_SROUTING_MSP430_TC232 1
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#define CPLD_SROUTING_MSP430_GSM 2
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#define CPLD_SROUTING_LOON_LPR (0 << 4)
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#define CPLD_SROUTING_LOON_TC232 (1 << 4)
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#define CPLD_SROUTING_LOON_GSM (2 << 4)
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#define CPLD_AROUTING_SET 0x0c
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#define CPLD_AROUTING_CLR 0x1c
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#define CPLD_AROUTING_MIC2PHONE_BIT 0
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#define CPLD_AROUTING_PHONE2INT_BIT 1
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#define CPLD_AROUTING_PHONE2EXT_BIT 2
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#define CPLD_AROUTING_LOONL2INT_BIT 3
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#define CPLD_AROUTING_LOONL2EXT_BIT 4
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#define CPLD_AROUTING_LOONR2PHONE_BIT 5
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#define CPLD_AROUTING_LOONR2INT_BIT 6
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#define CPLD_AROUTING_LOONR2EXT_BIT 7
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/* Balloon3 Interrupts */
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#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x))
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#define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
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#define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
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#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16)
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extern int balloon3_has(enum balloon3_features feature);
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#endif
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