681 lines
21 KiB
C
681 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/asm/kvm_host.h:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#ifndef __ARM64_KVM_HOST_H__
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#define __ARM64_KVM_HOST_H__
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/jump_label.h>
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#include <linux/kvm_types.h>
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#include <linux/percpu.h>
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#include <asm/arch_gicv3.h>
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#include <asm/barrier.h>
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#include <asm/cpufeature.h>
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#include <asm/cputype.h>
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#include <asm/daifflags.h>
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#include <asm/fpsimd.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/thread_info.h>
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED
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#define KVM_USER_MEM_SLOTS 512
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#define KVM_HALT_POLL_NS_DEFAULT 500000
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#include <kvm/arm_vgic.h>
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#include <kvm/arm_arch_timer.h>
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#include <kvm/arm_pmu.h>
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#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
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#define KVM_VCPU_MAX_FEATURES 7
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#define KVM_REQ_SLEEP \
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KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
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#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
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#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
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DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
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extern unsigned int kvm_sve_max_vl;
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int kvm_arm_init_sve(void);
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int __attribute_const__ kvm_target_cpu(void);
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
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void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu);
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int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext);
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void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
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struct kvm_vmid {
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/* The VMID generation used for the virt. memory system */
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u64 vmid_gen;
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u32 vmid;
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};
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struct kvm_arch {
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struct kvm_vmid vmid;
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/* stage2 entry level table */
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pgd_t *pgd;
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phys_addr_t pgd_phys;
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/* VTCR_EL2 value for this VM */
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u64 vtcr;
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/* The last vcpu id that ran on each physical CPU */
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int __percpu *last_vcpu_ran;
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/* The maximum number of vCPUs depends on the used GIC model */
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int max_vcpus;
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/* Interrupt controller */
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struct vgic_dist vgic;
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/* Mandated version of PSCI */
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u32 psci_version;
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};
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#define KVM_NR_MEM_OBJS 40
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/*
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* We don't want allocation failures within the mmu code, so we preallocate
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* enough memory for a single page fault in a cache.
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*/
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struct kvm_mmu_memory_cache {
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int nobjs;
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void *objects[KVM_NR_MEM_OBJS];
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};
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struct kvm_vcpu_fault_info {
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u32 esr_el2; /* Hyp Syndrom Register */
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u64 far_el2; /* Hyp Fault Address Register */
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u64 hpfar_el2; /* Hyp IPA Fault Address Register */
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u64 disr_el1; /* Deferred [SError] Status Register */
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};
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/*
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* 0 is reserved as an invalid value.
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* Order should be kept in sync with the save/restore code.
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*/
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enum vcpu_sysreg {
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__INVALID_SYSREG__,
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MPIDR_EL1, /* MultiProcessor Affinity Register */
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CSSELR_EL1, /* Cache Size Selection Register */
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SCTLR_EL1, /* System Control Register */
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ACTLR_EL1, /* Auxiliary Control Register */
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CPACR_EL1, /* Coprocessor Access Control */
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ZCR_EL1, /* SVE Control */
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TTBR0_EL1, /* Translation Table Base Register 0 */
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TTBR1_EL1, /* Translation Table Base Register 1 */
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TCR_EL1, /* Translation Control Register */
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ESR_EL1, /* Exception Syndrome Register */
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AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
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AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
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FAR_EL1, /* Fault Address Register */
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MAIR_EL1, /* Memory Attribute Indirection Register */
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VBAR_EL1, /* Vector Base Address Register */
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CONTEXTIDR_EL1, /* Context ID Register */
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TPIDR_EL0, /* Thread ID, User R/W */
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TPIDRRO_EL0, /* Thread ID, User R/O */
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TPIDR_EL1, /* Thread ID, Privileged */
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AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
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CNTKCTL_EL1, /* Timer Control Register (EL1) */
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PAR_EL1, /* Physical Address Register */
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MDSCR_EL1, /* Monitor Debug System Control Register */
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MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
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DISR_EL1, /* Deferred Interrupt Status Register */
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/* Performance Monitors Registers */
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PMCR_EL0, /* Control Register */
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PMSELR_EL0, /* Event Counter Selection Register */
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PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
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PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
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PMCCNTR_EL0, /* Cycle Counter Register */
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PMEVTYPER0_EL0, /* Event Type Register (0-30) */
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PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
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PMCCFILTR_EL0, /* Cycle Count Filter Register */
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PMCNTENSET_EL0, /* Count Enable Set Register */
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PMINTENSET_EL1, /* Interrupt Enable Set Register */
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PMOVSSET_EL0, /* Overflow Flag Status Set Register */
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PMSWINC_EL0, /* Software Increment Register */
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PMUSERENR_EL0, /* User Enable Register */
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/* Pointer Authentication Registers in a strict increasing order. */
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APIAKEYLO_EL1,
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APIAKEYHI_EL1,
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APIBKEYLO_EL1,
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APIBKEYHI_EL1,
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APDAKEYLO_EL1,
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APDAKEYHI_EL1,
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APDBKEYLO_EL1,
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APDBKEYHI_EL1,
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APGAKEYLO_EL1,
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APGAKEYHI_EL1,
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/* 32bit specific registers. Keep them at the end of the range */
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DACR32_EL2, /* Domain Access Control Register */
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IFSR32_EL2, /* Instruction Fault Status Register */
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FPEXC32_EL2, /* Floating-Point Exception Control Register */
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DBGVCR32_EL2, /* Debug Vector Catch Register */
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NR_SYS_REGS /* Nothing after this line! */
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};
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/* 32bit mapping */
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#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
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#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
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#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
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#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
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#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
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#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
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#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
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#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
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#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
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#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
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#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
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#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
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#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
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#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
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#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
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#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
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#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
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#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
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#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
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#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
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#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
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#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
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#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
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#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
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#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
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#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
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#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
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#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
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#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
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#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
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#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
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#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
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#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
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#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
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#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
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#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
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#define NR_COPRO_REGS (NR_SYS_REGS * 2)
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struct kvm_cpu_context {
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struct kvm_regs gp_regs;
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union {
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u64 sys_regs[NR_SYS_REGS];
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u32 copro[NR_COPRO_REGS];
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};
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struct kvm_vcpu *__hyp_running_vcpu;
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};
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struct kvm_pmu_events {
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u32 events_host;
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u32 events_guest;
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};
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struct kvm_host_data {
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struct kvm_cpu_context host_ctxt;
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struct kvm_pmu_events pmu_events;
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};
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typedef struct kvm_host_data kvm_host_data_t;
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struct vcpu_reset_state {
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unsigned long pc;
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unsigned long r0;
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bool be;
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bool reset;
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};
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struct kvm_vcpu_arch {
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struct kvm_cpu_context ctxt;
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void *sve_state;
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unsigned int sve_max_vl;
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/* HYP configuration */
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u64 hcr_el2;
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u32 mdcr_el2;
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/* Exception Information */
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struct kvm_vcpu_fault_info fault;
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/* State of various workarounds, see kvm_asm.h for bit assignment */
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u64 workaround_flags;
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/* Miscellaneous vcpu state flags */
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u64 flags;
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/*
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* We maintain more than a single set of debug registers to support
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* debugging the guest from the host and to maintain separate host and
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* guest state during world switches. vcpu_debug_state are the debug
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* registers of the vcpu as the guest sees them. host_debug_state are
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* the host registers which are saved and restored during
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* world switches. external_debug_state contains the debug
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* values we want to debug the guest. This is set via the
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* KVM_SET_GUEST_DEBUG ioctl.
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*
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* debug_ptr points to the set of debug registers that should be loaded
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* onto the hardware when running the guest.
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*/
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struct kvm_guest_debug_arch *debug_ptr;
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struct kvm_guest_debug_arch vcpu_debug_state;
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struct kvm_guest_debug_arch external_debug_state;
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/* Pointer to host CPU context */
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struct kvm_cpu_context *host_cpu_context;
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struct thread_info *host_thread_info; /* hyp VA */
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struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
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struct {
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/* {Break,watch}point registers */
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struct kvm_guest_debug_arch regs;
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/* Statistical profiling extension */
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u64 pmscr_el1;
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} host_debug_state;
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/* VGIC state */
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struct vgic_cpu vgic_cpu;
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struct arch_timer_cpu timer_cpu;
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struct kvm_pmu pmu;
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/*
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* Anything that is not used directly from assembly code goes
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* here.
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*/
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/*
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* Guest registers we preserve during guest debugging.
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*
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* These shadow registers are updated by the kvm_handle_sys_reg
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* trap handler if the guest accesses or updates them while we
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* are using guest debug.
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*/
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struct {
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u32 mdscr_el1;
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} guest_debug_preserved;
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/* vcpu power-off state */
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bool power_off;
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/* Don't run the guest (internal implementation need) */
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bool pause;
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/* IO related fields */
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struct kvm_decode mmio_decode;
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/* Cache some mmu pages needed inside spinlock regions */
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struct kvm_mmu_memory_cache mmu_page_cache;
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/* Target CPU and feature flags */
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int target;
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DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
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/* Detect first run of a vcpu */
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bool has_run_once;
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/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
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u64 vsesr_el2;
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/* Additional reset state */
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struct vcpu_reset_state reset_state;
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/* True when deferrable sysregs are loaded on the physical CPU,
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* see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
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bool sysregs_loaded_on_cpu;
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};
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/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
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#define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \
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sve_ffr_offset((vcpu)->arch.sve_max_vl)))
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#define vcpu_sve_state_size(vcpu) ({ \
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size_t __size_ret; \
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unsigned int __vcpu_vq; \
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\
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if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
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__size_ret = 0; \
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} else { \
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__vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \
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__size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
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} \
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\
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__size_ret; \
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})
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/* vcpu_arch flags field values: */
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#define KVM_ARM64_DEBUG_DIRTY (1 << 0)
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#define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */
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#define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */
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#define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */
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#define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */
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#define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */
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#define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */
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#define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */
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#define vcpu_has_sve(vcpu) (system_supports_sve() && \
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((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE))
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#define vcpu_has_ptrauth(vcpu) ((system_supports_address_auth() || \
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system_supports_generic_auth()) && \
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((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH))
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#define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
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/*
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* Only use __vcpu_sys_reg if you know you want the memory backed version of a
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* register, and not the one most recently accessed by a running VCPU. For
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* example, for userspace access or for system registers that are never context
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* switched, but only emulated.
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*/
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#define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
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u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
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void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
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/*
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* CP14 and CP15 live in the same array, as they are backed by the
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* same system registers.
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*/
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#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
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#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
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struct kvm_vm_stat {
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ulong remote_tlb_flush;
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};
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struct kvm_vcpu_stat {
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u64 halt_successful_poll;
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u64 halt_attempted_poll;
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u64 halt_poll_invalid;
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u64 halt_wakeup;
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u64 hvc_exit_stat;
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u64 wfe_exit_stat;
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u64 wfi_exit_stat;
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u64 mmio_exit_user;
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u64 mmio_exit_kernel;
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u64 exits;
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};
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int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
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unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
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int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
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int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
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int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
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struct kvm_vcpu_events *events);
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int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
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struct kvm_vcpu_events *events);
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#define KVM_ARCH_WANT_MMU_NOTIFIER
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int kvm_unmap_hva_range(struct kvm *kvm,
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unsigned long start, unsigned long end);
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int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
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int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
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int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
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struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
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struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
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void kvm_arm_halt_guest(struct kvm *kvm);
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void kvm_arm_resume_guest(struct kvm *kvm);
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|
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u64 __kvm_call_hyp(void *hypfn, ...);
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|
|
|
/*
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* The couple of isb() below are there to guarantee the same behaviour
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* on VHE as on !VHE, where the eret to EL1 acts as a context
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|
* synchronization event.
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|
*/
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#define kvm_call_hyp(f, ...) \
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do { \
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if (has_vhe()) { \
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f(__VA_ARGS__); \
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isb(); \
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|
} else { \
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__kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \
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|
} \
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|
} while(0)
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|
|
|
#define kvm_call_hyp_ret(f, ...) \
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({ \
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typeof(f(__VA_ARGS__)) ret; \
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|
\
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|
if (has_vhe()) { \
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|
ret = f(__VA_ARGS__); \
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|
isb(); \
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|
} else { \
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ret = __kvm_call_hyp(kvm_ksym_ref(f), \
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|
##__VA_ARGS__); \
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} \
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\
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|
ret; \
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|
})
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|
|
|
void force_vm_exit(const cpumask_t *mask);
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|
void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
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|
|
|
int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
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|
int exception_index);
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|
void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
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|
int exception_index);
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|
|
|
int kvm_perf_init(void);
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|
int kvm_perf_teardown(void);
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|
|
|
void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
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|
|
|
struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
|
|
|
|
DECLARE_PER_CPU(kvm_host_data_t, kvm_host_data);
|
|
|
|
static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
|
|
{
|
|
/* The host's MPIDR is immutable, so let's set it up at boot time */
|
|
cpu_ctxt->sys_regs[MPIDR_EL1] = read_cpuid_mpidr();
|
|
}
|
|
|
|
void __kvm_enable_ssbs(void);
|
|
|
|
static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
|
|
unsigned long hyp_stack_ptr,
|
|
unsigned long vector_ptr)
|
|
{
|
|
/*
|
|
* Calculate the raw per-cpu offset without a translation from the
|
|
* kernel's mapping to the linear mapping, and store it in tpidr_el2
|
|
* so that we can use adr_l to access per-cpu variables in EL2.
|
|
*/
|
|
u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_data) -
|
|
(u64)kvm_ksym_ref(kvm_host_data));
|
|
|
|
/*
|
|
* Call initialization code, and switch to the full blown HYP code.
|
|
* If the cpucaps haven't been finalized yet, something has gone very
|
|
* wrong, and hyp will crash and burn when it uses any
|
|
* cpus_have_const_cap() wrapper.
|
|
*/
|
|
BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
|
|
__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
|
|
|
|
/*
|
|
* Disabling SSBD on a non-VHE system requires us to enable SSBS
|
|
* at EL2.
|
|
*/
|
|
if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
|
|
arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
|
|
kvm_call_hyp(__kvm_enable_ssbs);
|
|
}
|
|
}
|
|
|
|
static inline bool kvm_arch_requires_vhe(void)
|
|
{
|
|
/*
|
|
* The Arm architecture specifies that implementation of SVE
|
|
* requires VHE also to be implemented. The KVM code for arm64
|
|
* relies on this when SVE is present:
|
|
*/
|
|
if (system_supports_sve())
|
|
return true;
|
|
|
|
/* Some implementations have defects that confine them to VHE */
|
|
if (cpus_have_cap(ARM64_WORKAROUND_1165522))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
|
|
|
|
static inline void kvm_arch_hardware_unsetup(void) {}
|
|
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
|
|
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
|
|
static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
|
|
|
|
void kvm_arm_init_debug(void);
|
|
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
|
|
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
|
|
void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
|
|
int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
|
|
struct kvm_device_attr *attr);
|
|
int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
|
|
struct kvm_device_attr *attr);
|
|
int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
|
|
struct kvm_device_attr *attr);
|
|
|
|
static inline void __cpu_init_stage2(void) {}
|
|
|
|
/* Guest/host FPSIMD coordination helpers */
|
|
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
|
|
void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
|
|
void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
|
|
void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
|
|
|
|
static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
|
|
{
|
|
return (!has_vhe() && attr->exclude_host);
|
|
}
|
|
|
|
#ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
|
|
static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
|
|
{
|
|
return kvm_arch_vcpu_run_map_fp(vcpu);
|
|
}
|
|
|
|
void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
|
|
void kvm_clr_pmu_events(u32 clr);
|
|
|
|
void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
|
|
void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
|
|
#else
|
|
static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
|
|
static inline void kvm_clr_pmu_events(u32 clr) {}
|
|
#endif
|
|
|
|
static inline void kvm_arm_vhe_guest_enter(void)
|
|
{
|
|
local_daif_mask();
|
|
|
|
/*
|
|
* Having IRQs masked via PMR when entering the guest means the GIC
|
|
* will not signal the CPU of interrupts of lower priority, and the
|
|
* only way to get out will be via guest exceptions.
|
|
* Naturally, we want to avoid this.
|
|
*
|
|
* local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
|
|
* dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
|
|
*/
|
|
if (system_uses_irq_prio_masking())
|
|
dsb(sy);
|
|
}
|
|
|
|
static inline void kvm_arm_vhe_guest_exit(void)
|
|
{
|
|
/*
|
|
* local_daif_restore() takes care to properly restore PSTATE.DAIF
|
|
* and the GIC PMR if the host is using IRQ priorities.
|
|
*/
|
|
local_daif_restore(DAIF_PROCCTX_NOIRQ);
|
|
|
|
/*
|
|
* When we exit from the guest we change a number of CPU configuration
|
|
* parameters, such as traps. Make sure these changes take effect
|
|
* before running the host or additional guests.
|
|
*/
|
|
isb();
|
|
}
|
|
|
|
#define KVM_BP_HARDEN_UNKNOWN -1
|
|
#define KVM_BP_HARDEN_WA_NEEDED 0
|
|
#define KVM_BP_HARDEN_NOT_REQUIRED 1
|
|
|
|
static inline int kvm_arm_harden_branch_predictor(void)
|
|
{
|
|
switch (get_spectre_v2_workaround_state()) {
|
|
case ARM64_BP_HARDEN_WA_NEEDED:
|
|
return KVM_BP_HARDEN_WA_NEEDED;
|
|
case ARM64_BP_HARDEN_NOT_REQUIRED:
|
|
return KVM_BP_HARDEN_NOT_REQUIRED;
|
|
case ARM64_BP_HARDEN_UNKNOWN:
|
|
default:
|
|
return KVM_BP_HARDEN_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
#define KVM_SSBD_UNKNOWN -1
|
|
#define KVM_SSBD_FORCE_DISABLE 0
|
|
#define KVM_SSBD_KERNEL 1
|
|
#define KVM_SSBD_FORCE_ENABLE 2
|
|
#define KVM_SSBD_MITIGATED 3
|
|
|
|
static inline int kvm_arm_have_ssbd(void)
|
|
{
|
|
switch (arm64_get_ssbd_state()) {
|
|
case ARM64_SSBD_FORCE_DISABLE:
|
|
return KVM_SSBD_FORCE_DISABLE;
|
|
case ARM64_SSBD_KERNEL:
|
|
return KVM_SSBD_KERNEL;
|
|
case ARM64_SSBD_FORCE_ENABLE:
|
|
return KVM_SSBD_FORCE_ENABLE;
|
|
case ARM64_SSBD_MITIGATED:
|
|
return KVM_SSBD_MITIGATED;
|
|
case ARM64_SSBD_UNKNOWN:
|
|
default:
|
|
return KVM_SSBD_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
|
|
void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
|
|
|
|
void kvm_set_ipa_limit(void);
|
|
|
|
#define __KVM_HAVE_ARCH_VM_ALLOC
|
|
struct kvm *kvm_arch_alloc_vm(void);
|
|
void kvm_arch_free_vm(struct kvm *kvm);
|
|
|
|
int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
|
|
|
|
int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
|
|
bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
|
|
|
|
#define kvm_arm_vcpu_sve_finalized(vcpu) \
|
|
((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED)
|
|
|
|
#endif /* __ARM64_KVM_HOST_H__ */
|