166 lines
3.6 KiB
C
166 lines
3.6 KiB
C
/*
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* linux/include/asm-arm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_ATOMIC_H
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#define __ASM_ARM_ATOMIC_H
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#include <linux/config.h>
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typedef struct { volatile int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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#define atomic_read(v) ((v)->counter)
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#if __LINUX_ARM_ARCH__ >= 6
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/*
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* ARMv6 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens. Writing to 'v->counter'
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* without using the following operations WILL break the atomic
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* nature of these ops.
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*/
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static inline void atomic_set(atomic_t *v, int i)
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{
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unsigned long tmp;
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__asm__ __volatile__("@ atomic_set\n"
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"1: ldrex %0, [%1]\n"
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" strex %0, %2, [%1]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&v->counter), "r" (i)
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: "cc");
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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__asm__ __volatile__("@ atomic_add_return\n"
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"1: ldrex %0, [%2]\n"
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" add %0, %0, %3\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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return result;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long tmp;
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int result;
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__asm__ __volatile__("@ atomic_sub_return\n"
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"1: ldrex %0, [%2]\n"
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" sub %0, %0, %3\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (result), "=&r" (tmp)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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return result;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__("@ atomic_clear_mask\n"
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"1: ldrex %0, %2\n"
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" bic %0, %0, %3\n"
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" strex %1, %0, %2\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (addr), "Ir" (mask)
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: "cc");
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}
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#else /* ARM_ARCH_6 */
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#include <asm/system.h>
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#ifdef CONFIG_SMP
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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#define atomic_set(v,i) (((v)->counter) = (i))
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long flags;
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int val;
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local_irq_save(flags);
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val = v->counter;
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v->counter = val += i;
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local_irq_restore(flags);
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return val;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long flags;
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int val;
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local_irq_save(flags);
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val = v->counter;
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v->counter = val -= i;
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local_irq_restore(flags);
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return val;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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unsigned long flags;
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local_irq_save(flags);
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*addr &= ~mask;
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local_irq_restore(flags);
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}
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#endif /* __LINUX_ARM_ARCH__ */
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#define atomic_add(i, v) (void) atomic_add_return(i, v)
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#define atomic_inc(v) (void) atomic_add_return(1, v)
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#define atomic_sub(i, v) (void) atomic_sub_return(i, v)
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#define atomic_dec(v) (void) atomic_sub_return(1, v)
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#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
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#define atomic_inc_return(v) (atomic_add_return(1, v))
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#define atomic_dec_return(v) (atomic_sub_return(1, v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
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/* Atomic operations are already serializing on ARM */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#endif
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#endif
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