263 lines
8.3 KiB
C
263 lines
8.3 KiB
C
/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright 2002 H. Peter Anvin - All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Bostom MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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/*
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* raid6sse2.c
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*
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* SSE-2 implementation of RAID-6 syndrome functions
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*
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#include "raid6.h"
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#include "raid6x86.h"
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static const struct raid6_sse_constants {
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u64 x1d[2];
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} raid6_sse_constants __attribute__((aligned(16))) = {
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{ 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL },
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};
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static int raid6_have_sse2(void)
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{
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/* Not really boot_cpu but "all_cpus" */
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return boot_cpu_has(X86_FEATURE_MMX) &&
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boot_cpu_has(X86_FEATURE_FXSR) &&
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boot_cpu_has(X86_FEATURE_XMM) &&
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boot_cpu_has(X86_FEATURE_XMM2);
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}
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/*
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* Plain SSE2 implementation
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*/
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static void raid6_sse21_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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for ( d = 0 ; d < bytes ; d += 16 ) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
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asm volatile("movdqa %0,%%xmm2" : : "m" (dptr[z0][d])); /* P[0] */
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asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d]));
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asm volatile("movdqa %xmm2,%xmm4"); /* Q[0] */
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asm volatile("movdqa %0,%%xmm6" : : "m" (dptr[z0-1][d]));
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for ( z = z0-2 ; z >= 0 ; z-- ) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("pcmpgtb %xmm4,%xmm5");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("pand %xmm0,%xmm5");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm5,%xmm5");
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asm volatile("pxor %xmm6,%xmm2");
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asm volatile("pxor %xmm6,%xmm4");
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asm volatile("movdqa %0,%%xmm6" : : "m" (dptr[z][d]));
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}
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asm volatile("pcmpgtb %xmm4,%xmm5");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("pand %xmm0,%xmm5");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm5,%xmm5");
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asm volatile("pxor %xmm6,%xmm2");
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asm volatile("pxor %xmm6,%xmm4");
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d]));
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asm volatile("pxor %xmm2,%xmm2");
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asm volatile("movntdq %%xmm4,%0" : "=m" (q[d]));
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asm volatile("pxor %xmm4,%xmm4");
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse2x1 = {
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raid6_sse21_gen_syndrome,
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raid6_have_sse2,
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"sse2x1",
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1 /* Has cache hints */
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};
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/*
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* Unrolled-by-2 SSE2 implementation
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*/
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static void raid6_sse22_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("movdqa %0,%%xmm0" : : "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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asm volatile("pxor %xmm7,%xmm7"); /* Zero temp */
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/* We uniformly assume a single prefetch covers at least 32 bytes */
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for ( d = 0 ; d < bytes ; d += 32 ) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
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asm volatile("movdqa %0,%%xmm2" : : "m" (dptr[z0][d])); /* P[0] */
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asm volatile("movdqa %0,%%xmm3" : : "m" (dptr[z0][d+16])); /* P[1] */
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asm volatile("movdqa %xmm2,%xmm4"); /* Q[0] */
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asm volatile("movdqa %xmm3,%xmm6"); /* Q[1] */
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for ( z = z0-1 ; z >= 0 ; z-- ) {
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asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("pcmpgtb %xmm4,%xmm5");
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asm volatile("pcmpgtb %xmm6,%xmm7");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("paddb %xmm6,%xmm6");
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asm volatile("pand %xmm0,%xmm5");
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asm volatile("pand %xmm0,%xmm7");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("movdqa %0,%%xmm5" : : "m" (dptr[z][d]));
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asm volatile("movdqa %0,%%xmm7" : : "m" (dptr[z][d+16]));
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asm volatile("pxor %xmm5,%xmm2");
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asm volatile("pxor %xmm7,%xmm3");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("pxor %xmm5,%xmm5");
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asm volatile("pxor %xmm7,%xmm7");
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}
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d]));
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asm volatile("movntdq %%xmm3,%0" : "=m" (p[d+16]));
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asm volatile("movntdq %%xmm4,%0" : "=m" (q[d]));
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asm volatile("movntdq %%xmm6,%0" : "=m" (q[d+16]));
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse2x2 = {
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raid6_sse22_gen_syndrome,
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raid6_have_sse2,
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"sse2x2",
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1 /* Has cache hints */
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};
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#endif
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#ifdef __x86_64__
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/*
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* Unrolled-by-4 SSE2 implementation
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*/
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static void raid6_sse24_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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kernel_fpu_begin();
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asm volatile("movdqa %0,%%xmm0" :: "m" (raid6_sse_constants.x1d[0]));
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asm volatile("pxor %xmm2,%xmm2"); /* P[0] */
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asm volatile("pxor %xmm3,%xmm3"); /* P[1] */
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asm volatile("pxor %xmm4,%xmm4"); /* Q[0] */
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asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
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asm volatile("pxor %xmm6,%xmm6"); /* Q[1] */
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asm volatile("pxor %xmm7,%xmm7"); /* Zero temp */
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asm volatile("pxor %xmm10,%xmm10"); /* P[2] */
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asm volatile("pxor %xmm11,%xmm11"); /* P[3] */
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asm volatile("pxor %xmm12,%xmm12"); /* Q[2] */
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asm volatile("pxor %xmm13,%xmm13"); /* Zero temp */
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asm volatile("pxor %xmm14,%xmm14"); /* Q[3] */
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asm volatile("pxor %xmm15,%xmm15"); /* Zero temp */
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for ( d = 0 ; d < bytes ; d += 64 ) {
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for ( z = z0 ; z >= 0 ; z-- ) {
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/* The second prefetch seems to improve performance... */
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asm volatile("prefetchnta %0" :: "m" (dptr[z][d]));
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asm volatile("prefetchnta %0" :: "m" (dptr[z][d+32]));
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asm volatile("pcmpgtb %xmm4,%xmm5");
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asm volatile("pcmpgtb %xmm6,%xmm7");
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asm volatile("pcmpgtb %xmm12,%xmm13");
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asm volatile("pcmpgtb %xmm14,%xmm15");
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asm volatile("paddb %xmm4,%xmm4");
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asm volatile("paddb %xmm6,%xmm6");
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asm volatile("paddb %xmm12,%xmm12");
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asm volatile("paddb %xmm14,%xmm14");
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asm volatile("pand %xmm0,%xmm5");
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asm volatile("pand %xmm0,%xmm7");
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asm volatile("pand %xmm0,%xmm13");
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asm volatile("pand %xmm0,%xmm15");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("pxor %xmm13,%xmm12");
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asm volatile("pxor %xmm15,%xmm14");
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asm volatile("movdqa %0,%%xmm5" :: "m" (dptr[z][d]));
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asm volatile("movdqa %0,%%xmm7" :: "m" (dptr[z][d+16]));
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asm volatile("movdqa %0,%%xmm13" :: "m" (dptr[z][d+32]));
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asm volatile("movdqa %0,%%xmm15" :: "m" (dptr[z][d+48]));
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asm volatile("pxor %xmm5,%xmm2");
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asm volatile("pxor %xmm7,%xmm3");
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asm volatile("pxor %xmm13,%xmm10");
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asm volatile("pxor %xmm15,%xmm11");
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asm volatile("pxor %xmm5,%xmm4");
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asm volatile("pxor %xmm7,%xmm6");
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asm volatile("pxor %xmm13,%xmm12");
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asm volatile("pxor %xmm15,%xmm14");
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asm volatile("pxor %xmm5,%xmm5");
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asm volatile("pxor %xmm7,%xmm7");
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asm volatile("pxor %xmm13,%xmm13");
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asm volatile("pxor %xmm15,%xmm15");
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}
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asm volatile("movntdq %%xmm2,%0" : "=m" (p[d]));
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asm volatile("pxor %xmm2,%xmm2");
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asm volatile("movntdq %%xmm3,%0" : "=m" (p[d+16]));
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asm volatile("pxor %xmm3,%xmm3");
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asm volatile("movntdq %%xmm10,%0" : "=m" (p[d+32]));
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asm volatile("pxor %xmm10,%xmm10");
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asm volatile("movntdq %%xmm11,%0" : "=m" (p[d+48]));
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asm volatile("pxor %xmm11,%xmm11");
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asm volatile("movntdq %%xmm4,%0" : "=m" (q[d]));
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asm volatile("pxor %xmm4,%xmm4");
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asm volatile("movntdq %%xmm6,%0" : "=m" (q[d+16]));
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asm volatile("pxor %xmm6,%xmm6");
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asm volatile("movntdq %%xmm12,%0" : "=m" (q[d+32]));
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asm volatile("pxor %xmm12,%xmm12");
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asm volatile("movntdq %%xmm14,%0" : "=m" (q[d+48]));
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asm volatile("pxor %xmm14,%xmm14");
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}
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asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
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}
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const struct raid6_calls raid6_sse2x4 = {
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raid6_sse24_gen_syndrome,
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raid6_have_sse2,
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"sse2x4",
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1 /* Has cache hints */
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};
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#endif
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