427 lines
12 KiB
C
427 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) Icenowy Zheng <icenowy@aosc.io>
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*
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* Based on sun4i_layer.h, which is:
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_gem_atomic_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_probe_helper.h>
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#include "sun8i_mixer.h"
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#include "sun8i_ui_layer.h"
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#include "sun8i_ui_scaler.h"
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static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
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int overlay, bool enable, unsigned int zpos,
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unsigned int old_zpos)
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{
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u32 val, bld_base, ch_base;
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bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
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enable ? "En" : "Dis", channel, overlay);
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if (enable)
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val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
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if (!enable || zpos != old_zpos) {
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
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0);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ROUTE(bld_base),
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SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
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0);
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}
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if (enable) {
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val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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val, val);
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val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ROUTE(bld_base),
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SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
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val);
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}
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}
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static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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u32 mask, val, ch_base;
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ch_base = sun8i_channel_base(mixer, channel);
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mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK |
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK;
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val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA(plane->state->alpha >> 8);
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val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ?
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_PIXEL :
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
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mask, val);
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}
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static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane,
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unsigned int zpos)
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{
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struct drm_plane_state *state = plane->state;
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u32 src_w, src_h, dst_w, dst_h;
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u32 bld_base, ch_base;
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u32 outsize, insize;
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u32 hphase, vphase;
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DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
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channel, overlay);
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bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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src_w = drm_rect_width(&state->src) >> 16;
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src_h = drm_rect_height(&state->src) >> 16;
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dst_w = drm_rect_width(&state->dst);
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dst_h = drm_rect_height(&state->dst);
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hphase = state->src.x1 & 0xffff;
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vphase = state->src.y1 & 0xffff;
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insize = SUN8I_MIXER_SIZE(src_w, src_h);
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outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
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if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
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bool interlaced = false;
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u32 val;
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DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
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dst_w, dst_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_GLOBAL_SIZE,
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outsize);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize);
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if (state->crtc)
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interlaced = state->crtc->state->adjusted_mode.flags
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& DRM_MODE_FLAG_INTERLACE;
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if (interlaced)
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val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_OUTCTL(bld_base),
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SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
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val);
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DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
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interlaced ? "on" : "off");
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}
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/* Set height and width */
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DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
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state->src.x1 >> 16, state->src.y1 >> 16);
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DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
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insize);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
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insize);
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if (insize != outsize || hphase || vphase) {
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u32 hscale, vscale;
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DRM_DEBUG_DRIVER("HW scaling is enabled\n");
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hscale = state->src_w / state->crtc_w;
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vscale = state->src_h / state->crtc_h;
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sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
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dst_h, hscale, vscale, hphase, vphase);
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sun8i_ui_scaler_enable(mixer, channel, true);
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} else {
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DRM_DEBUG_DRIVER("HW scaling is not needed\n");
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sun8i_ui_scaler_enable(mixer, channel, false);
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}
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
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state->dst.x1, state->dst.y1);
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DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
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SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
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outsize);
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return 0;
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}
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static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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const struct drm_format_info *fmt;
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u32 val, ch_base, hw_fmt;
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int ret;
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ch_base = sun8i_channel_base(mixer, channel);
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fmt = state->fb->format;
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ret = sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt);
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if (ret || fmt->is_yuv) {
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DRM_DEBUG_DRIVER("Invalid format\n");
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return -EINVAL;
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}
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val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
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return 0;
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}
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static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct drm_gem_cma_object *gem;
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dma_addr_t paddr;
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u32 ch_base;
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int bpp;
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ch_base = sun8i_channel_base(mixer, channel);
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/* Get the physical address of the buffer in memory */
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
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/* Compute the start of the displayed memory */
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bpp = fb->format->cpp[0];
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paddr = gem->paddr + fb->offsets[0];
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/* Fixup framebuffer address for src coordinates */
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paddr += (state->src.x1 >> 16) * bpp;
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paddr += (state->src.y1 >> 16) * fb->pitches[0];
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/* Set the line width */
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DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
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fb->pitches[0]);
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DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
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lower_32_bits(paddr));
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return 0;
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}
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static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
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struct drm_crtc *crtc = new_plane_state->crtc;
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struct drm_crtc_state *crtc_state;
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int min_scale, max_scale;
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if (!crtc)
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return 0;
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crtc_state = drm_atomic_get_existing_crtc_state(state,
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crtc);
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if (WARN_ON(!crtc_state))
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return -EINVAL;
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min_scale = DRM_PLANE_HELPER_NO_SCALING;
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max_scale = DRM_PLANE_HELPER_NO_SCALING;
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if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
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min_scale = SUN8I_UI_SCALER_SCALE_MIN;
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max_scale = SUN8I_UI_SCALER_SCALE_MAX;
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}
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return drm_atomic_helper_check_plane_state(new_plane_state,
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crtc_state,
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min_scale, max_scale,
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true, true);
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}
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static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
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plane);
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struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
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unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
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old_zpos);
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}
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static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
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plane);
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struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
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unsigned int zpos = new_state->normalized_zpos;
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unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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if (!new_state->visible) {
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sun8i_ui_layer_enable(mixer, layer->channel,
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layer->overlay, false, 0, old_zpos);
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return;
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}
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sun8i_ui_layer_update_coord(mixer, layer->channel,
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layer->overlay, plane, zpos);
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sun8i_ui_layer_update_alpha(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_ui_layer_update_formats(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_ui_layer_update_buffer(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
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true, zpos, old_zpos);
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}
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static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
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.atomic_check = sun8i_ui_layer_atomic_check,
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.atomic_disable = sun8i_ui_layer_atomic_disable,
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.atomic_update = sun8i_ui_layer_atomic_update,
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};
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static const struct drm_plane_funcs sun8i_ui_layer_funcs = {
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.destroy = drm_plane_cleanup,
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.disable_plane = drm_atomic_helper_disable_plane,
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.reset = drm_atomic_helper_plane_reset,
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.update_plane = drm_atomic_helper_update_plane,
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};
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static const u32 sun8i_ui_layer_formats[] = {
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_ABGR4444,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_BGR565,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_BGRA5551,
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DRM_FORMAT_BGRA4444,
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DRM_FORMAT_BGRA8888,
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DRM_FORMAT_BGRX8888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_RGBA4444,
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DRM_FORMAT_RGBA5551,
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DRM_FORMAT_RGBA8888,
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DRM_FORMAT_RGBX8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888,
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};
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static const uint64_t sun8i_layer_modifiers[] = {
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DRM_FORMAT_MOD_LINEAR,
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DRM_FORMAT_MOD_INVALID
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};
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struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
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struct sun8i_mixer *mixer,
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int index)
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{
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enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
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int channel = mixer->cfg->vi_num + index;
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struct sun8i_ui_layer *layer;
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unsigned int plane_cnt;
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int ret;
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layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
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if (!layer)
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return ERR_PTR(-ENOMEM);
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if (index == 0)
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type = DRM_PLANE_TYPE_PRIMARY;
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/* possible crtcs are set later */
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ret = drm_universal_plane_init(drm, &layer->plane, 0,
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&sun8i_ui_layer_funcs,
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sun8i_ui_layer_formats,
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ARRAY_SIZE(sun8i_ui_layer_formats),
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sun8i_layer_modifiers, type, NULL);
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if (ret) {
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dev_err(drm->dev, "Couldn't initialize layer\n");
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return ERR_PTR(ret);
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}
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plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
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ret = drm_plane_create_alpha_property(&layer->plane);
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if (ret) {
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dev_err(drm->dev, "Couldn't add alpha property\n");
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return ERR_PTR(ret);
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}
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ret = drm_plane_create_zpos_property(&layer->plane, channel,
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0, plane_cnt - 1);
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if (ret) {
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dev_err(drm->dev, "Couldn't add zpos property\n");
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return ERR_PTR(ret);
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}
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drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
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layer->mixer = mixer;
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layer->channel = channel;
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layer->overlay = 0;
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return layer;
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}
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