535 lines
15 KiB
C
535 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// tegra210_adx.c - Tegra210 ADX driver
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//
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// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra210_adx.h"
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#include "tegra_cif.h"
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static const struct reg_default tegra210_adx_reg_defaults[] = {
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{ TEGRA210_ADX_RX_INT_MASK, 0x00000001},
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{ TEGRA210_ADX_RX_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_TX_INT_MASK, 0x0000000f },
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{ TEGRA210_ADX_TX1_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_TX2_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_TX3_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_TX4_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_CG, 0x1},
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{ TEGRA210_ADX_CFG_RAM_CTRL, 0x00004000},
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};
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static void tegra210_adx_write_map_ram(struct tegra210_adx *adx)
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{
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int i;
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regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_CTRL,
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TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
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TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN |
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TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE);
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for (i = 0; i < TEGRA210_ADX_RAM_DEPTH; i++)
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regmap_write(adx->regmap, TEGRA210_ADX_CFG_RAM_DATA,
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adx->map[i]);
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regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN0, adx->byte_mask[0]);
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regmap_write(adx->regmap, TEGRA210_ADX_IN_BYTE_EN1, adx->byte_mask[1]);
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}
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static int tegra210_adx_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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unsigned int val;
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int err;
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/* Ensure if ADX status is disabled */
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err = regmap_read_poll_timeout_atomic(adx->regmap, TEGRA210_ADX_STATUS,
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val, !(val & 0x1), 10, 10000);
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if (err < 0) {
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dev_err(dai->dev, "failed to stop ADX, err = %d\n", err);
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return err;
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}
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/*
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* Soft Reset: Below performs module soft reset which clears
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* all FSM logic, flushes flow control of FIFO and resets the
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* state register. It also brings module back to disabled
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* state (without flushing the data in the pipe).
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*/
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regmap_update_bits(adx->regmap, TEGRA210_ADX_SOFT_RESET,
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TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK,
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TEGRA210_ADX_SOFT_RESET_SOFT_EN);
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err = regmap_read_poll_timeout(adx->regmap, TEGRA210_ADX_SOFT_RESET,
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val, !(val & 0x1), 10, 10000);
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if (err < 0) {
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dev_err(dai->dev, "failed to reset ADX, err = %d\n", err);
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return err;
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}
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return 0;
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}
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static int __maybe_unused tegra210_adx_runtime_suspend(struct device *dev)
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{
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struct tegra210_adx *adx = dev_get_drvdata(dev);
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regcache_cache_only(adx->regmap, true);
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regcache_mark_dirty(adx->regmap);
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return 0;
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}
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static int __maybe_unused tegra210_adx_runtime_resume(struct device *dev)
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{
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struct tegra210_adx *adx = dev_get_drvdata(dev);
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regcache_cache_only(adx->regmap, false);
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regcache_sync(adx->regmap);
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tegra210_adx_write_map_ram(adx);
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return 0;
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}
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static int tegra210_adx_set_audio_cif(struct snd_soc_dai *dai,
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unsigned int channels,
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unsigned int format,
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unsigned int reg)
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{
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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struct tegra_cif_conf cif_conf;
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int audio_bits;
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
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if (channels < 1 || channels > 16)
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return -EINVAL;
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switch (format) {
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case SNDRV_PCM_FORMAT_S8:
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audio_bits = TEGRA_ACIF_BITS_8;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA_ACIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA_ACIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.audio_ch = channels;
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cif_conf.client_ch = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra_set_cif(adx->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_adx_out_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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return tegra210_adx_set_audio_cif(dai, params_channels(params),
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params_format(params),
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TEGRA210_ADX_TX1_CIF_CTRL + ((dai->id - 1) * TEGRA210_ADX_AUDIOCIF_CH_STRIDE));
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}
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static int tegra210_adx_in_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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return tegra210_adx_set_audio_cif(dai, params_channels(params),
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params_format(params),
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TEGRA210_ADX_RX_CIF_CTRL);
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}
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static int tegra210_adx_get_byte_map(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_adx *adx = snd_soc_component_get_drvdata(cmpnt);
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struct soc_mixer_control *mc;
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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int enabled;
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mc = (struct soc_mixer_control *)kcontrol->private_value;
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enabled = adx->byte_mask[mc->reg / 32] & (1 << (mc->reg % 32));
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if (enabled)
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ucontrol->value.integer.value[0] = bytes_map[mc->reg];
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else
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ucontrol->value.integer.value[0] = 0;
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return 0;
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}
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static int tegra210_adx_put_byte_map(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_adx *adx = snd_soc_component_get_drvdata(cmpnt);
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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int value = ucontrol->value.integer.value[0];
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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if (value == bytes_map[mc->reg])
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return 0;
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if (value >= 0 && value <= 255) {
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/* update byte map and enable slot */
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bytes_map[mc->reg] = value;
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adx->byte_mask[mc->reg / 32] |= (1 << (mc->reg % 32));
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} else {
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/* reset byte map and disable slot */
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bytes_map[mc->reg] = 0;
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adx->byte_mask[mc->reg / 32] &= ~(1 << (mc->reg % 32));
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}
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return 1;
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}
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static const struct snd_soc_dai_ops tegra210_adx_in_dai_ops = {
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.hw_params = tegra210_adx_in_hw_params,
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.startup = tegra210_adx_startup,
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};
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static const struct snd_soc_dai_ops tegra210_adx_out_dai_ops = {
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.hw_params = tegra210_adx_out_hw_params,
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};
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#define IN_DAI \
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{ \
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.name = "ADX-RX-CIF", \
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.playback = { \
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.stream_name = "RX-CIF-Playback", \
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = SNDRV_PCM_RATE_8000_192000, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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.capture = { \
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.stream_name = "RX-CIF-Capture", \
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = SNDRV_PCM_RATE_8000_192000, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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.ops = &tegra210_adx_in_dai_ops, \
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}
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#define OUT_DAI(id) \
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{ \
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.name = "ADX-TX" #id "-CIF", \
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.playback = { \
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.stream_name = "TX" #id "-CIF-Playback",\
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = SNDRV_PCM_RATE_8000_192000, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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.capture = { \
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.stream_name = "TX" #id "-CIF-Capture", \
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = SNDRV_PCM_RATE_8000_192000, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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.ops = &tegra210_adx_out_dai_ops, \
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}
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static struct snd_soc_dai_driver tegra210_adx_dais[] = {
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IN_DAI,
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OUT_DAI(1),
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OUT_DAI(2),
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OUT_DAI(3),
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OUT_DAI(4),
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};
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static const struct snd_soc_dapm_widget tegra210_adx_widgets[] = {
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SND_SOC_DAPM_AIF_IN("RX", NULL, 0, TEGRA210_ADX_ENABLE,
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TEGRA210_ADX_ENABLE_SHIFT, 0),
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SND_SOC_DAPM_AIF_OUT("TX1", NULL, 0, TEGRA210_ADX_CTRL, 0, 0),
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SND_SOC_DAPM_AIF_OUT("TX2", NULL, 0, TEGRA210_ADX_CTRL, 1, 0),
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SND_SOC_DAPM_AIF_OUT("TX3", NULL, 0, TEGRA210_ADX_CTRL, 2, 0),
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SND_SOC_DAPM_AIF_OUT("TX4", NULL, 0, TEGRA210_ADX_CTRL, 3, 0),
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};
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#define STREAM_ROUTES(id, sname) \
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{ "XBAR-" sname, NULL, "XBAR-TX" }, \
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{ "RX-CIF-" sname, NULL, "XBAR-" sname }, \
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{ "RX", NULL, "RX-CIF-" sname }, \
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{ "TX" #id, NULL, "RX" }, \
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{ "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
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{ "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
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{ "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname }
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#define ADX_ROUTES(id) \
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STREAM_ROUTES(id, "Playback"), \
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STREAM_ROUTES(id, "Capture")
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#define STREAM_ROUTES(id, sname) \
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{ "XBAR-" sname, NULL, "XBAR-TX" }, \
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{ "RX-CIF-" sname, NULL, "XBAR-" sname }, \
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{ "RX", NULL, "RX-CIF-" sname }, \
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{ "TX" #id, NULL, "RX" }, \
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{ "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
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{ "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
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{ "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname }
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#define ADX_ROUTES(id) \
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STREAM_ROUTES(id, "Playback"), \
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STREAM_ROUTES(id, "Capture")
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static const struct snd_soc_dapm_route tegra210_adx_routes[] = {
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ADX_ROUTES(1),
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ADX_ROUTES(2),
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ADX_ROUTES(3),
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ADX_ROUTES(4),
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};
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#define TEGRA210_ADX_BYTE_MAP_CTRL(reg) \
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SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \
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tegra210_adx_get_byte_map, \
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tegra210_adx_put_byte_map)
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static struct snd_kcontrol_new tegra210_adx_controls[] = {
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TEGRA210_ADX_BYTE_MAP_CTRL(0),
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TEGRA210_ADX_BYTE_MAP_CTRL(1),
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TEGRA210_ADX_BYTE_MAP_CTRL(2),
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TEGRA210_ADX_BYTE_MAP_CTRL(3),
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TEGRA210_ADX_BYTE_MAP_CTRL(4),
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TEGRA210_ADX_BYTE_MAP_CTRL(5),
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TEGRA210_ADX_BYTE_MAP_CTRL(6),
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TEGRA210_ADX_BYTE_MAP_CTRL(7),
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TEGRA210_ADX_BYTE_MAP_CTRL(8),
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TEGRA210_ADX_BYTE_MAP_CTRL(9),
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TEGRA210_ADX_BYTE_MAP_CTRL(10),
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TEGRA210_ADX_BYTE_MAP_CTRL(11),
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TEGRA210_ADX_BYTE_MAP_CTRL(12),
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TEGRA210_ADX_BYTE_MAP_CTRL(13),
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TEGRA210_ADX_BYTE_MAP_CTRL(14),
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TEGRA210_ADX_BYTE_MAP_CTRL(15),
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TEGRA210_ADX_BYTE_MAP_CTRL(16),
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TEGRA210_ADX_BYTE_MAP_CTRL(17),
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TEGRA210_ADX_BYTE_MAP_CTRL(18),
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TEGRA210_ADX_BYTE_MAP_CTRL(19),
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TEGRA210_ADX_BYTE_MAP_CTRL(20),
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TEGRA210_ADX_BYTE_MAP_CTRL(21),
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TEGRA210_ADX_BYTE_MAP_CTRL(22),
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TEGRA210_ADX_BYTE_MAP_CTRL(23),
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TEGRA210_ADX_BYTE_MAP_CTRL(24),
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TEGRA210_ADX_BYTE_MAP_CTRL(25),
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TEGRA210_ADX_BYTE_MAP_CTRL(26),
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TEGRA210_ADX_BYTE_MAP_CTRL(27),
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TEGRA210_ADX_BYTE_MAP_CTRL(28),
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TEGRA210_ADX_BYTE_MAP_CTRL(29),
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TEGRA210_ADX_BYTE_MAP_CTRL(30),
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TEGRA210_ADX_BYTE_MAP_CTRL(31),
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TEGRA210_ADX_BYTE_MAP_CTRL(32),
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TEGRA210_ADX_BYTE_MAP_CTRL(33),
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TEGRA210_ADX_BYTE_MAP_CTRL(34),
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TEGRA210_ADX_BYTE_MAP_CTRL(35),
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TEGRA210_ADX_BYTE_MAP_CTRL(36),
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TEGRA210_ADX_BYTE_MAP_CTRL(37),
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TEGRA210_ADX_BYTE_MAP_CTRL(38),
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TEGRA210_ADX_BYTE_MAP_CTRL(39),
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TEGRA210_ADX_BYTE_MAP_CTRL(40),
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TEGRA210_ADX_BYTE_MAP_CTRL(41),
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TEGRA210_ADX_BYTE_MAP_CTRL(42),
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TEGRA210_ADX_BYTE_MAP_CTRL(43),
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TEGRA210_ADX_BYTE_MAP_CTRL(44),
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TEGRA210_ADX_BYTE_MAP_CTRL(45),
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TEGRA210_ADX_BYTE_MAP_CTRL(46),
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TEGRA210_ADX_BYTE_MAP_CTRL(47),
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TEGRA210_ADX_BYTE_MAP_CTRL(48),
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TEGRA210_ADX_BYTE_MAP_CTRL(49),
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TEGRA210_ADX_BYTE_MAP_CTRL(50),
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TEGRA210_ADX_BYTE_MAP_CTRL(51),
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TEGRA210_ADX_BYTE_MAP_CTRL(52),
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TEGRA210_ADX_BYTE_MAP_CTRL(53),
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TEGRA210_ADX_BYTE_MAP_CTRL(54),
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TEGRA210_ADX_BYTE_MAP_CTRL(55),
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TEGRA210_ADX_BYTE_MAP_CTRL(56),
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TEGRA210_ADX_BYTE_MAP_CTRL(57),
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TEGRA210_ADX_BYTE_MAP_CTRL(58),
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TEGRA210_ADX_BYTE_MAP_CTRL(59),
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TEGRA210_ADX_BYTE_MAP_CTRL(60),
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TEGRA210_ADX_BYTE_MAP_CTRL(61),
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TEGRA210_ADX_BYTE_MAP_CTRL(62),
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TEGRA210_ADX_BYTE_MAP_CTRL(63),
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};
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static const struct snd_soc_component_driver tegra210_adx_cmpnt = {
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.dapm_widgets = tegra210_adx_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_adx_widgets),
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.dapm_routes = tegra210_adx_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_adx_routes),
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.controls = tegra210_adx_controls,
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.num_controls = ARRAY_SIZE(tegra210_adx_controls),
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};
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static bool tegra210_adx_wr_reg(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_ADX_TX_INT_MASK ... TEGRA210_ADX_TX4_CIF_CTRL:
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case TEGRA210_ADX_RX_INT_MASK ... TEGRA210_ADX_RX_CIF_CTRL:
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case TEGRA210_ADX_ENABLE ... TEGRA210_ADX_CG:
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case TEGRA210_ADX_CTRL ... TEGRA210_ADX_IN_BYTE_EN1:
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case TEGRA210_ADX_CFG_RAM_CTRL ... TEGRA210_ADX_CFG_RAM_DATA:
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return true;
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default:
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return false;
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}
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}
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static bool tegra210_adx_rd_reg(struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case TEGRA210_ADX_RX_STATUS ... TEGRA210_ADX_CFG_RAM_DATA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool tegra210_adx_volatile_reg(struct device *dev,
|
|
unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_ADX_RX_STATUS:
|
|
case TEGRA210_ADX_RX_INT_STATUS:
|
|
case TEGRA210_ADX_RX_INT_SET:
|
|
case TEGRA210_ADX_TX_STATUS:
|
|
case TEGRA210_ADX_TX_INT_STATUS:
|
|
case TEGRA210_ADX_TX_INT_SET:
|
|
case TEGRA210_ADX_SOFT_RESET:
|
|
case TEGRA210_ADX_STATUS:
|
|
case TEGRA210_ADX_INT_STATUS:
|
|
case TEGRA210_ADX_CFG_RAM_CTRL:
|
|
case TEGRA210_ADX_CFG_RAM_DATA:
|
|
return true;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static const struct regmap_config tegra210_adx_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA210_ADX_CFG_RAM_DATA,
|
|
.writeable_reg = tegra210_adx_wr_reg,
|
|
.readable_reg = tegra210_adx_rd_reg,
|
|
.volatile_reg = tegra210_adx_volatile_reg,
|
|
.reg_defaults = tegra210_adx_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(tegra210_adx_reg_defaults),
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static const struct of_device_id tegra210_adx_of_match[] = {
|
|
{ .compatible = "nvidia,tegra210-adx" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra210_adx_of_match);
|
|
|
|
static int tegra210_adx_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct tegra210_adx *adx;
|
|
void __iomem *regs;
|
|
int err;
|
|
|
|
adx = devm_kzalloc(dev, sizeof(*adx), GFP_KERNEL);
|
|
if (!adx)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, adx);
|
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
adx->regmap = devm_regmap_init_mmio(dev, regs,
|
|
&tegra210_adx_regmap_config);
|
|
if (IS_ERR(adx->regmap)) {
|
|
dev_err(dev, "regmap init failed\n");
|
|
return PTR_ERR(adx->regmap);
|
|
}
|
|
|
|
regcache_cache_only(adx->regmap, true);
|
|
|
|
err = devm_snd_soc_register_component(dev, &tegra210_adx_cmpnt,
|
|
tegra210_adx_dais,
|
|
ARRAY_SIZE(tegra210_adx_dais));
|
|
if (err) {
|
|
dev_err(dev, "can't register ADX component, err: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_adx_platform_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra210_adx_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra210_adx_runtime_suspend,
|
|
tegra210_adx_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra210_adx_driver = {
|
|
.driver = {
|
|
.name = "tegra210-adx",
|
|
.of_match_table = tegra210_adx_of_match,
|
|
.pm = &tegra210_adx_pm_ops,
|
|
},
|
|
.probe = tegra210_adx_platform_probe,
|
|
.remove = tegra210_adx_platform_remove,
|
|
};
|
|
module_platform_driver(tegra210_adx_driver);
|
|
|
|
MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra210 ADX ASoC driver");
|
|
MODULE_LICENSE("GPL v2");
|