OpenCloudOS-Kernel/Documentation/arm64
Suzuki K Poulose 8d81b2a38d arm64: errata: Add detection for TRBE write to out-of-range
Arm Neoverse-N2 and Cortex-A710 cores are affected by an erratum where
the trbe, under some circumstances, might write upto 64bytes to an
address after the Limit as programmed by the TRBLIMITR_EL1.LIMIT.
This might -
  - Corrupt a page in the ring buffer, which may corrupt trace from a
    previous session, consumed by userspace.
  - Hit the guard page at the end of the vmalloc area and raise a fault.

To keep the handling simpler, we always leave the last page from the
range, which TRBE is allowed to write. This can be achieved by ensuring
that we always have more than a PAGE worth space in the range, while
calculating the LIMIT for TRBE. And then the LIMIT pointer can be
adjusted to leave the PAGE (TRBLIMITR.LIMIT -= PAGE_SIZE), out of the
TRBE range while enabling it. This makes sure that the TRBE will only
write to an area within its allowed limit (i.e, [head-head+size]) and
we do not have to handle address faults within the driver.

Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20211019163153.3692640-5-suzuki.poulose@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
2021-10-21 17:49:17 +01:00
..
acpi_object_usage.rst Documentation: arm64/acpi : clarify arm64 support of IBFT 2021-03-22 12:43:20 +00:00
amu.rst Documentation: Chinese translation of Documentation/arm64/amu.rst 2020-09-28 15:24:24 -06:00
arm-acpi.rst arm64: Replace HTTP links with HTTPS ones 2020-07-23 14:04:37 -06:00
asymmetric-32bit.rst Documentation: arm64: describe asymmetric 32-bit support 2021-08-20 12:33:07 +02:00
booting.rst arm64: Document the requirement for SCR_EL3.HCE 2021-08-24 16:44:23 +01:00
cpu-feature-registers.rst arm64: mte: Add Memory Tagging Extension documentation 2020-09-04 12:46:07 +01:00
elf_hwcaps.rst arm64: Fix the documented event stream frequency 2021-05-05 18:34:28 +01:00
features.rst docs: archis: add a per-architecture features list 2020-12-03 15:10:15 -07:00
hugetlbpage.rst Documentation: Chinese translation of Documentation/arm64/hugetlbpage.rst 2020-10-21 15:15:17 -06:00
index.rst Documentation: arm64: describe asymmetric 32-bit support 2021-08-20 12:33:07 +02:00
kasan-offsets.sh arm64: mm: extend linear region for 52-bit VA configurations 2020-11-09 17:15:37 +00:00
legacy_instructions.rst docs: arm64: convert docs to ReST and rename to .rst 2019-06-14 14:20:27 -06:00
memory-tagging-extension.rst Documentation: document the preferred tag checking mode feature 2021-07-28 18:39:26 +01:00
memory.rst ARM: 2020-12-20 10:44:05 -08:00
perf.rst Documentation: Chinese translation of Documentation/arm64/perf.rst 2020-11-13 15:21:38 -07:00
pointer-authentication.rst arm64: Introduce prctl(PR_PAC_{SET,GET}_ENABLED_KEYS) 2021-04-13 17:31:44 +01:00
silicon-errata.rst arm64: errata: Add detection for TRBE write to out-of-range 2021-10-21 17:49:17 +01:00
sve.rst It's been a busy cycle for documentation - hopefully the busiest for a 2020-08-04 22:47:54 -07:00
tagged-address-abi.rst userfaultfd: do not untag user pointers 2021-07-23 17:43:28 -07:00
tagged-pointers.rst arm64: expose FAR_EL1 tag bits in siginfo 2020-11-23 18:17:39 +00:00