121 lines
3.2 KiB
YAML
121 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g043-ssi # RZ/G2UL
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- renesas,r9a07g044-ssi # RZ/G2{L,LC}
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- renesas,r9a07g054-ssi # RZ/V2L
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- const: renesas,rz-ssi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 4
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interrupt-names:
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items:
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- const: int_req
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- const: dma_rx
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- const: dma_tx
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- const: dma_rt
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: ssi
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- const: ssi_sfr
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- const: audio_clk1
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- const: audio_clk2
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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dmas:
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minItems: 1
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maxItems: 2
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description:
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The first cell represents a phandle to dmac.
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The second cell specifies the encoded MID/RID values of the SSI port
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connected to the DMA client and the slave channel configuration
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parameters.
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bits[0:9] - Specifies MID/RID value of a SSI channel as below
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MID/RID value of SSI rx0 = 0x256
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MID/RID value of SSI tx0 = 0x255
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MID/RID value of SSI rx1 = 0x25a
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MID/RID value of SSI tx1 = 0x259
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MID/RID value of SSI rt2 = 0x25f
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MID/RID value of SSI rx3 = 0x262
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MID/RID value of SSI tx3 = 0x261
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bit[10] - HIEN = 1, Detects a request in response to the rising edge
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of the signal
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bit[11] - LVL = 0, Detects based on the edge
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bits[12:14] - AM = 2, Bus cycle mode
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bit[15] - TM = 0, Single transfer mode
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dma-names:
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oneOf:
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- items:
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- const: tx
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- const: rx
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- items:
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- const: rt
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'#sound-dai-cells':
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const: 0
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- '#sound-dai-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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ssi0: ssi@10049c00 {
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compatible = "renesas,r9a07g044-ssi",
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"renesas,rz-ssi";
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reg = <0x10049c00 0x400>;
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interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
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clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
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<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
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<&audio_clk1>,
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<&audio_clk2>;
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clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
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dmas = <&dmac 0x2655>,
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<&dmac 0x2656>;
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dma-names = "tx", "rx";
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#sound-dai-cells = <0>;
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};
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