64 lines
1.9 KiB
Plaintext
64 lines
1.9 KiB
Plaintext
BROADCOM Cygnus Audio I2S/TDM/SPDIF controller
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Required properties:
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- compatible : "brcm,cygnus-audio"
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- #address-cells: 32bit valued, 1 cell.
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- #size-cells: 32bit valued, 0 cell.
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- reg : Should contain audio registers location and length
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- reg-names: names of the registers listed in "reg" property
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Valid names are "aud" and "i2s_in". "aud" contains a
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set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains
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a set of I2S_IN registers.
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- clocks: PLL and leaf clocks used by audio ports
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- assigned-clocks: PLL and leaf clocks
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- assigned-clock-parents: parent clocks of the assigned clocks
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(usually the PLL)
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- assigned-clock-rates: List of clock frequencies of the
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assigned clocks
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- clock-names: names of 3 leaf clocks used by audio ports
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Valid names are "ch0_audio", "ch1_audio", "ch2_audio"
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- interrupts: audio DMA interrupt number
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SSP Subnode properties:
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- reg: The index of ssp port interface to use
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Valid value are 0, 1, 2, or 3 (for spdif)
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Example:
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cygnus_audio: audio@180ae000 {
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compatible = "brcm,cygnus-audio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>;
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reg-names = "aud", "i2s_in";
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clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
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<&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
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<&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
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assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
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<&audiopll BCM_CYGNUS_AUDIOPLL_CH0>,
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<&audiopll BCM_CYGNUS_AUDIOPLL_CH1>,
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<&audiopll BCM_CYGNUS_AUDIOPLL_CH2>;
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assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
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assigned-clock-rates = <1769470191>,
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<0>,
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<0>,
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<0>;
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clock-names = "ch0_audio", "ch1_audio", "ch2_audio";
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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ssp0: ssp_port@0 {
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reg = <0>;
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};
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ssp1: ssp_port@1 {
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reg = <1>;
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};
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ssp2: ssp_port@2 {
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reg = <2>;
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};
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spdif: spdif_port@3 {
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reg = <3>;
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};
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};
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