133 lines
5.4 KiB
Plaintext
133 lines
5.4 KiB
Plaintext
Adaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs
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Required Properties:
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- compatible: Should be one of:
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- "ti,abb-v1" for older SoCs like OMAP3
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- "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
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- "ti,abb-v3" for a generic definition where setup and control registers are
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provided (example: DRA7)
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- reg: Address and length of the register set for the device. It contains
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the information of registers in the same order as described by reg-names
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- reg-names: Should contain the reg names
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- "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
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- "control-address" - contains control register address of ABB module (ti,abb-v3)
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- "setup-address" - contains setup register address of ABB module (ti,abb-v3)
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- "int-address" - contains address of interrupt register for ABB module
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(also see Optional properties)
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- #address-cells: should be 0
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- #size-cells: should be 0
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- clocks: should point to the clock node used by ABB module
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- ti,settling-time: Settling time in uSecs from SoC documentation for ABB module
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to settle down(target time for SR2_WTCNT_VALUE).
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- ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
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computing settling time from SoC Documentation for ABB module(clock
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cycles for SR2_WTCNT_VALUE).
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- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
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indicating LDO tranxdone (operation complete).
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- ti,abb_info: An array of 6-tuples u32 items providing information about ABB
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configuration needed per operational voltage of the device.
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Each item consists of the following in the same order:
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volt: voltage in uV - Only used to index ABB information.
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ABB mode: one of the following:
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0-bypass
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1-Forward Body Bias(FBB)
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3-Reverse Body Bias(RBB)
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efuse: (see Optional properties)
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RBB enable efuse Mask: (See Optional properties)
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FBB enable efuse Mask: (See Optional properties)
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Vset value efuse Mask: (See Optional properties)
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NOTE: If more than 1 entry is present, then regulator is setup to change
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voltage, allowing for various modes to be selected indexed off
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the regulator. Further, ABB LDOs are considered always-on by
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default.
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Optional Properties:
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- reg-names: In addition to the required properties, the following are optional
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- "efuse-address" - Contains efuse base address used to pick up ABB info.
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- "ldo-address" - Contains address of ABB LDO override register.
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"efuse-address" is required for this.
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- ti,ldovbb-vset-mask - Required if ldo-address is set, mask for LDO override
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register to provide override vset value.
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- ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO
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override register to enable override vset value.
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- ti,abb_opp_sel: Addendum to the description in required properties
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efuse: Mandatory if 'efuse-address' register is defined. Provides offset
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from efuse-address to pick up ABB characteristics. Set to 0 if
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'efuse-address' is not defined.
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RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
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'ABB mode' is force set to RBB mode if value at "efuse-address"
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+ efuse maps to RBB mask. Set to 0 to ignore this.
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FBB enable efuse Mask: Optional if 'efuse-address' register is defined.
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'ABB mode' is force set to FBB mode if value at "efuse-address"
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+ efuse maps to FBB mask (valid only if RBB mask does not match)
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Set to 0 to ignore this.
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Vset value efuse Mask: Mandatory if ldo-address is set. Picks up from
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efuse the value to set in 'ti,ldovbb-vset-mask' at ldo-address.
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Example #1: Simplest configuration (no efuse data, hard coded ABB table):
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abb_x: regulator-abb-x {
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compatible = "ti,abb-v1";
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regulator-name = "abb_x";
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#address-cells = <0>;
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#size-cells = <0>;
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reg = <0x483072f0 0x8>, <0x48306818 0x4>;
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reg-names = "base-address", "int-address";
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ti,tranxdone-status-mask = <0x4000000>;
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clocks = <&sysclk>;
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ti,settling-time = <30>;
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ti,clock-cycles = <8>;
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ti,abb_info = <
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/* uV ABB efuse rbb_m fbb_m vset_m */
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1012500 0 0 0 0 0 /* Bypass */
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1200000 3 0 0 0 0 /* RBB mandatory */
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1320000 1 0 0 0 0 /* FBB mandatory */
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>;
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};
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Example #2: Efuse bits contain ABB mode setting (no LDO override capability)
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abb_y: regulator-abb-y {
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compatible = "ti,abb-v2";
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regulator-name = "abb_y";
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#address-cells = <0>;
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#size-cells = <0>;
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reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>;
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reg-names = "base-address", "int-address", "efuse-address";
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ti,tranxdone-status-mask = <0x4000000>;
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clocks = <&sysclk>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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ti,abb_info = <
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/* uV ABB efuse rbb_m fbb_m vset_m */
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975000 0 0 0 0 0 /* Bypass */
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1012500 0 0 0x40000 0 0 /* RBB optional */
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1200000 0 0x4 0 0x40000 0 /* FBB optional */
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1320000 1 0 0 0 0 /* FBB mandatory */
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>;
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};
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Example #3: Efuse bits contain ABB mode setting and LDO override capability
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abb_z: regulator-abb-z {
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compatible = "ti,abb-v2";
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regulator-name = "abb_z";
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#address-cells = <0>;
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#size-cells = <0>;
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reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
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<0x4a002194 0x8>, <0x4ae0C314 0x4>;
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reg-names = "base-address", "int-address",
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"efuse-address", "ldo-address";
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ti,tranxdone-status-mask = <0x8000000>;
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/* LDOVBBMM_MUX_CTRL */
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ti,ldovbb-override-mask = <0x400>;
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/* LDOVBBMM_VSET_OUT */
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ti,ldovbb-vset-mask = <0x1F>;
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clocks = <&sysclk>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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ti,abb_info = <
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/* uV ABB efuse rbb_m fbb_m vset_m */
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975000 0 0 0 0 0 /* Bypass */
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1200000 0 0x4 0 0x40000 0x1f00 /* FBB optional, vset */
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>;
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};
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