200 lines
6.8 KiB
Plaintext
200 lines
6.8 KiB
Plaintext
Qualcomm QCS404 TLMM block
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This binding describes the Top Level Mode Multiplexer block found in the
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QCS404 platform.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,qcs404-pinctrl"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the north, south and east TLMM
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tiles.
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- reg-names:
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Usage: required
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Value type: <stringlist>
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Defintiion: names for the cells of reg, must contain "north", "south"
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and "east".
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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- interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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- gpio-ranges:
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Usage: required
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Definition: see ../gpio/gpio.txt
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode.
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Valid pins are:
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gpio0-gpio119
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Supports mux, bias and drive-strength
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sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
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sdc2_data
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Supports bias and drive-strength
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ufs_reset
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Supports bias and drive-strength
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values are:
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gpio, hdmi_tx, hdmi_ddc, blsp_uart_tx_a2, blsp_spi2, m_voc,
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qdss_cti_trig_in_a0, blsp_uart_rx_a2, qdss_tracectl_a,
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blsp_uart2, aud_cdc, blsp_i2c_sda_a2, qdss_tracedata_a,
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blsp_i2c_scl_a2, qdss_tracectl_b, qdss_cti_trig_in_b0,
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blsp_uart1, blsp_spi_mosi_a1, blsp_spi_miso_a1,
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qdss_tracedata_b, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest,
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blsp_spi_clk_a1, rgb_data0, blsp_uart5, blsp_spi5,
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adsp_ext, rgb_data1, prng_rosc, rgb_data2, blsp_i2c5,
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gcc_gp1_clk_b, rgb_data3, gcc_gp2_clk_b, blsp_spi0,
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blsp_uart0, gcc_gp3_clk_b, blsp_i2c0, qdss_traceclk_b,
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pcie_clk, nfc_irq, blsp_spi4, nfc_dwl, audio_ts, rgb_data4,
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spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, rgb_data5,
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blsp_uart_rx_b2, blsp_i2c_sda_b2, blsp_i2c_scl_b2,
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pwm_led11, i2s_3_data0_a, ebi2_lcd, i2s_3_data1_a,
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i2s_3_data2_a, atest_char, pwm_led3, i2s_3_data3_a,
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pwm_led4, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, pwm_led6,
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pwm_led7, pwm_led8, pwm_led24, spkr_dac0, blsp_i2c4,
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pwm_led9, pwm_led10, spdifrx_opt, pwm_led12, pwm_led13,
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pwm_led14, wlan1_adc1, rgb_data_b0, pwm_led15,
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blsp_spi_mosi_b1, wlan1_adc0, rgb_data_b1, pwm_led16,
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blsp_spi_miso_b1, qdss_cti_trig_out_b0, wlan2_adc1,
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rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, wlan2_adc0,
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rgb_data_b3, pwm_led18, blsp_spi_clk_b1, rgb_data_b4,
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pwm_led19, ext_mclk1_b, qdss_traceclk_a, rgb_data_b5,
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pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0,
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rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, rgb_vsync,
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i2s_3_data0_b, ldo_en, hdmi_dtest, rgb_de, i2s_3_data1_b,
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hdmi_lbk9, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc,
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hdmi_lbk8, rgb_mdp, atest_char0, i2s_3_data3_b, hdmi_lbk7,
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rgb_data_b6, rgb_data_b7, hdmi_lbk6, rgmii_int, cri_trng1,
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rgmii_wol, cri_trng0, gcc_tlmm, rgmii_ck, rgmii_tx,
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hdmi_lbk5, hdmi_pixel, hdmi_rcv, hdmi_lbk4, rgmii_ctl,
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ext_lpass, rgmii_rx, cri_trng, hdmi_lbk3, hdmi_lbk2,
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qdss_cti_trig_out_b1, rgmii_mdio, hdmi_lbk1, rgmii_mdc,
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hdmi_lbk0, ir_in, wsa_en, rgb_data6, rgb_data7,
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atest_char2, ebi_ch0, blsp_uart3, blsp_spi3, sd_write,
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blsp_i2c3, gcc_gp1_clk_a, qdss_cti_trig_in_b1,
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gcc_gp2_clk_a, ext_mclk0, mclk_in1, i2s_1, dsd_clk_a,
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qdss_cti_trig_in_a1, rgmi_dll1, pwm_led22, pwm_led23,
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qdss_cti_trig_out_a0, rgmi_dll2, pwm_led1,
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qdss_cti_trig_out_a1, pwm_led2, i2s_2, pll_bist,
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ext_mclk1_a, mclk_in2, bimc_dte1, i2s_3_sck_a, i2s_3_ws_a
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configured as pull up.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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Not valid for sdc pins.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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Not valid for sdc pins.
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- drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
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Example:
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tlmm: pinctrl@1000000 {
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compatible = "qcom,qcs404-pinctrl";
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reg = <0x01000000 0x200000>,
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<0x01300000 0x200000>,
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<0x07b00000 0x200000>;
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reg-names = "south", "north", "east";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 120>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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