205 lines
10 KiB
Plaintext
205 lines
10 KiB
Plaintext
Actions Semi S900 Pin Controller
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This binding describes the pin controller found in the S900 SoC.
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Required Properties:
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- compatible: Should be "actions,s900-pinctrl"
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- reg: Should contain the register base address and size of
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the pin controller.
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- clocks: phandle of the clock feeding the pin controller
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- gpio-controller: Marks the device node as a GPIO controller.
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- gpio-ranges: Specifies the mapping between gpio controller and
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pin-controller pins.
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- #gpio-cells: Should be two. The first cell is the gpio pin number
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and the second cell is used for optional parameters.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt. Shall be set to 2. The first cell
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defines the interrupt number, the second encodes
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the trigger flags described in
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bindings/interrupt-controller/interrupts.txt
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- interrupts: The interrupt outputs from the controller. There is one GPIO
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interrupt per GPIO bank. The number of interrupts listed depends
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on the number of GPIO banks on the SoC. The interrupts must be
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ordered by bank, starting with bank 0.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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Pinmux functions are available only for the pin groups while pinconf
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parameters are available for both pin groups and individual pins.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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Required Properties:
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- pins: An array of strings, each string containing the name of a pin.
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These pins are used for selecting the pull control and schmitt
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trigger parameters. The following are the list of pins
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available:
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eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
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eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
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sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
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i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
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pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
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eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
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lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
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lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
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lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
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lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
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sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
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sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
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spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
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uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
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uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
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uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
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i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
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csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
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csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
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dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
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csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
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sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
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nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
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nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
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nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
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nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
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nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
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nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
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- groups: An array of strings, each string containing the name of a pin
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group. These pin groups are used for selecting the pinmux
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functions.
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lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
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sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
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rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
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rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
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i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
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pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
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eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
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eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
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lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
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spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
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uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
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sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
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uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
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csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
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dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
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nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
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csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
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These pin groups are used for selecting the drive strength
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parameters.
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sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
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rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
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rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
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sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
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i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
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lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
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sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
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spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
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uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
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These pin groups are used for selecting the slew rate
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parameters.
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sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
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rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
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rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
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i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
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pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
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spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
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uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
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sensor0_sr
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- function: An array of strings, each string containing the name of the
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pinmux functions. These functions can only be selected by
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the corresponding pin groups. The following are the list of
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pinmux functions available:
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eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
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uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
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pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
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sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
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usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
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nand1, spdif, sirq0, sirq1, sirq2
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Optional Properties:
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- bias-bus-hold: No arguments. The specified pins should retain the previous
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state value.
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- bias-high-impedance: No arguments. The specified pins should be configured
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as high impedance.
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- bias-pull-down: No arguments. The specified pins should be configured as
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pull down.
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- bias-pull-up: No arguments. The specified pins should be configured as
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pull up.
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- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
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pins
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- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
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pins
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- slew-rate: Integer. Sets slew rate for the specified pins.
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Valid values are:
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<0> - Slow
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<1> - Fast
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- drive-strength: Integer. Selects the drive strength for the specified
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pins in mA.
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Valid values are:
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<2>
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<4>
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<8>
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<12>
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Example:
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s900-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 146>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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uart2-default: uart2-default {
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pinmux {
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groups = "lvds_oep_odn_mfp";
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function = "uart2";
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};
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pinconf {
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groups = "lvds_oep_odn_drv";
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drive-strength = <12>;
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};
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};
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};
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