65 lines
2.0 KiB
Plaintext
65 lines
2.0 KiB
Plaintext
NVIDIA Tegra NAND Flash controller
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Required properties:
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- compatible: Must be one of:
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- "nvidia,tegra20-nand"
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- reg: MMIO address range
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- interrupts: interrupt output of the NFC controller
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- nand
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- nand
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Optional children nodes:
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Individual NAND chips are children of the NAND controller node. Currently
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only one NAND chip supported.
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Required children node properties:
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- reg: An integer ranging from 1 to 6 representing the CS line to use.
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Optional children node properties:
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- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
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"hw" is supported.
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- nand-ecc-algo: string, algorithm of NAND ECC.
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Supported values with "hw" ECC mode are: "rs", "bch".
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- nand-bus-width : See nand-controller.yaml
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- nand-on-flash-bbt: See nand-controller.yaml
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- nand-ecc-strength: integer representing the number of bits to correct
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per ECC step (always 512). Supported strength using HW ECC
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modes are:
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- RS: 4, 6, 8
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- BCH: 4, 8, 14, 16
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- nand-ecc-maximize: See nand-controller.yaml
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- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
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are chosen.
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- wp-gpios: GPIO specifier for the write protect pin.
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Optional child node of NAND chip nodes:
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Partitions: see partition.txt
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Example:
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nand-controller@70008000 {
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compatible = "nvidia,tegra20-nand";
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reg = <0x70008000 0x100>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
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clock-names = "nand";
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resets = <&tegra_car 13>;
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reset-names = "nand";
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nand@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-bus-width = <8>;
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nand-on-flash-bbt;
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nand-ecc-algo = "bch";
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nand-ecc-strength = <8>;
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wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
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};
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};
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