645 lines
16 KiB
C
645 lines
16 KiB
C
/*
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* bfin_sdh.c - Analog Devices Blackfin SDH Controller
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*
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* Copyright (C) 2007-2009 Analog Device Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#define DRIVER_NAME "bfin-sdh"
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <linux/proc_fs.h>
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#include <linux/gfp.h>
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#include <asm/cacheflush.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#include <asm/bfin_sdh.h>
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#if defined(CONFIG_BF51x)
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#define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
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#define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
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#define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
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#define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
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#define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
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#define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
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#define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
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#define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
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#define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
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#define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
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#define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
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#define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
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#define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CTL
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#define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CTL
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#define bfin_read_SDH_DATA_CNT bfin_read_RSI_DATA_CNT
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#define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUS_CLR
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#define bfin_read_SDH_E_STATUS bfin_read_RSI_E_STATUS
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#define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
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#define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
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#define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
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#define bfin_read_SDH_CFG bfin_read_RSI_CFG
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#define bfin_write_SDH_CFG bfin_write_RSI_CFG
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#endif
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struct dma_desc_array {
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unsigned long start_addr;
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unsigned short cfg;
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unsigned short x_count;
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short x_modify;
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} __packed;
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struct sdh_host {
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struct mmc_host *mmc;
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spinlock_t lock;
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struct resource *res;
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void __iomem *base;
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int irq;
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int stat_irq;
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int dma_ch;
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int dma_dir;
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struct dma_desc_array *sg_cpu;
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dma_addr_t sg_dma;
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int dma_len;
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unsigned int imask;
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unsigned int power_mode;
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unsigned int clk_div;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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};
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static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
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{
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return pdev->dev.platform_data;
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}
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static void sdh_stop_clock(struct sdh_host *host)
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{
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bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
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SSYNC();
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}
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static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask |= mask;
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bfin_write_SDH_MASK0(mask);
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SSYNC();
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask &= ~mask;
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bfin_write_SDH_MASK0(host->imask);
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SSYNC();
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
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{
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unsigned int length;
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unsigned int data_ctl;
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unsigned int dma_cfg;
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unsigned int cycle_ns, timeout;
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dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
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host->data = data;
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data_ctl = 0;
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dma_cfg = 0;
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length = data->blksz * data->blocks;
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bfin_write_SDH_DATA_LGTH(length);
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if (data->flags & MMC_DATA_STREAM)
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data_ctl |= DTX_MODE;
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if (data->flags & MMC_DATA_READ)
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data_ctl |= DTX_DIR;
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/* Only supports power-of-2 block size */
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if (data->blksz & (data->blksz - 1))
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return -EINVAL;
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data_ctl |= ((ffs(data->blksz) - 1) << 4);
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bfin_write_SDH_DATA_CTL(data_ctl);
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/* the time of a host clock period in ns */
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cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
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timeout = data->timeout_ns / cycle_ns;
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timeout += data->timeout_clks;
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bfin_write_SDH_DATA_TIMER(timeout);
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SSYNC();
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if (data->flags & MMC_DATA_READ) {
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host->dma_dir = DMA_FROM_DEVICE;
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dma_cfg |= WNR;
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} else
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host->dma_dir = DMA_TO_DEVICE;
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sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
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host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
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#if defined(CONFIG_BF54x)
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dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(data->sg, sg, host->dma_len, i) {
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host->sg_cpu[i].start_addr = sg_dma_address(sg);
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host->sg_cpu[i].cfg = dma_cfg;
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host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
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host->sg_cpu[i].x_modify = 4;
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dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
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"cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
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i, host->sg_cpu[i].start_addr,
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host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
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host->sg_cpu[i].x_modify);
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}
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}
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flush_dcache_range((unsigned int)host->sg_cpu,
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(unsigned int)host->sg_cpu +
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host->dma_len * sizeof(struct dma_desc_array));
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/* Set the last descriptor to stop mode */
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host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
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host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
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set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
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set_dma_x_count(host->dma_ch, 0);
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set_dma_x_modify(host->dma_ch, 0);
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set_dma_config(host->dma_ch, dma_cfg);
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#elif defined(CONFIG_BF51x)
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/* RSI DMA doesn't work in array mode */
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dma_cfg |= WDSIZE_32 | DMAEN;
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set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
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set_dma_x_count(host->dma_ch, length / 4);
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set_dma_x_modify(host->dma_ch, 4);
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set_dma_config(host->dma_ch, dma_cfg);
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#endif
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bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
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SSYNC();
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dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
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return 0;
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}
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static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
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{
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unsigned int sdh_cmd;
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unsigned int stat_mask;
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dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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sdh_cmd = 0;
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stat_mask = 0;
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sdh_cmd |= cmd->opcode;
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if (cmd->flags & MMC_RSP_PRESENT) {
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sdh_cmd |= CMD_RSP;
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stat_mask |= CMD_RESP_END;
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} else {
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stat_mask |= CMD_SENT;
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}
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if (cmd->flags & MMC_RSP_136)
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sdh_cmd |= CMD_L_RSP;
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stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
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sdh_enable_stat_irq(host, stat_mask);
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bfin_write_SDH_ARGUMENT(cmd->arg);
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bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
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bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
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SSYNC();
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}
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static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
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{
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dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
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host->mrq = NULL;
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host->cmd = NULL;
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host->data = NULL;
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mmc_request_done(host->mmc, mrq);
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}
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static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
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{
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struct mmc_command *cmd = host->cmd;
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int ret = 0;
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dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
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if (!cmd)
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return 0;
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host->cmd = NULL;
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if (cmd->flags & MMC_RSP_PRESENT) {
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cmd->resp[0] = bfin_read_SDH_RESPONSE0();
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if (cmd->flags & MMC_RSP_136) {
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cmd->resp[1] = bfin_read_SDH_RESPONSE1();
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cmd->resp[2] = bfin_read_SDH_RESPONSE2();
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cmd->resp[3] = bfin_read_SDH_RESPONSE3();
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}
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}
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if (stat & CMD_TIME_OUT)
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cmd->error = -ETIMEDOUT;
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else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
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cmd->error = -EILSEQ;
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sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
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if (host->data && !cmd->error) {
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if (host->data->flags & MMC_DATA_WRITE) {
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ret = sdh_setup_data(host, host->data);
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if (ret)
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return 0;
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}
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sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
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} else
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sdh_finish_request(host, host->mrq);
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return 1;
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}
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static int sdh_data_done(struct sdh_host *host, unsigned int stat)
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{
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struct mmc_data *data = host->data;
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dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
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if (!data)
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return 0;
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disable_dma(host->dma_ch);
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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host->dma_dir);
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if (stat & DAT_TIME_OUT)
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data->error = -ETIMEDOUT;
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else if (stat & DAT_CRC_FAIL)
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data->error = -EILSEQ;
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else if (stat & (RX_OVERRUN | TX_UNDERRUN))
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data->error = -EIO;
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if (!data->error)
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data->bytes_xfered = data->blocks * data->blksz;
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else
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data->bytes_xfered = 0;
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sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
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bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
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DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
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bfin_write_SDH_DATA_CTL(0);
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SSYNC();
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host->data = NULL;
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if (host->mrq->stop) {
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sdh_stop_clock(host);
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sdh_start_cmd(host, host->mrq->stop);
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} else {
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sdh_finish_request(host, host->mrq);
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}
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return 1;
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}
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static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct sdh_host *host = mmc_priv(mmc);
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int ret = 0;
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dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
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WARN_ON(host->mrq != NULL);
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host->mrq = mrq;
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host->data = mrq->data;
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if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
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ret = sdh_setup_data(host, mrq->data);
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if (ret)
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return;
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}
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sdh_start_cmd(host, mrq->cmd);
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}
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static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct sdh_host *host;
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unsigned long flags;
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u16 clk_ctl = 0;
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u16 pwr_ctl = 0;
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u16 cfg;
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host = mmc_priv(mmc);
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spin_lock_irqsave(&host->lock, flags);
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if (ios->clock) {
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unsigned long sys_clk, ios_clk;
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unsigned char clk_div;
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ios_clk = 2 * ios->clock;
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sys_clk = get_sclk();
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clk_div = sys_clk / ios_clk;
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if (sys_clk % ios_clk == 0)
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clk_div -= 1;
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clk_div = min_t(unsigned char, clk_div, 0xFF);
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clk_ctl |= clk_div;
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clk_ctl |= CLK_E;
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host->clk_div = clk_div;
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} else
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sdh_stop_clock(host);
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
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#ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
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pwr_ctl |= ROD_CTL;
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#else
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pwr_ctl |= SD_CMD_OD | ROD_CTL;
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#endif
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if (ios->bus_width == MMC_BUS_WIDTH_4) {
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cfg = bfin_read_SDH_CFG();
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cfg &= ~PD_SDDAT3;
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cfg |= PUP_SDDAT3;
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/* Enable 4 bit SDIO */
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cfg |= (SD4E | MWE);
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bfin_write_SDH_CFG(cfg);
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clk_ctl |= WIDE_BUS;
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} else {
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cfg = bfin_read_SDH_CFG();
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cfg |= MWE;
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bfin_write_SDH_CFG(cfg);
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}
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bfin_write_SDH_CLK_CTL(clk_ctl);
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host->power_mode = ios->power_mode;
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if (ios->power_mode == MMC_POWER_ON)
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pwr_ctl |= PWR_ON;
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bfin_write_SDH_PWR_CTL(pwr_ctl);
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SSYNC();
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spin_unlock_irqrestore(&host->lock, flags);
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dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
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host->clk_div,
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host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
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ios->clock);
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}
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static const struct mmc_host_ops sdh_ops = {
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.request = sdh_request,
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.set_ios = sdh_set_ios,
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};
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static irqreturn_t sdh_dma_irq(int irq, void *devid)
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{
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struct sdh_host *host = devid;
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dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
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get_dma_curr_irqstat(host->dma_ch));
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clear_dma_irqstat(host->dma_ch);
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SSYNC();
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return IRQ_HANDLED;
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}
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static irqreturn_t sdh_stat_irq(int irq, void *devid)
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{
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struct sdh_host *host = devid;
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unsigned int status;
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int handled = 0;
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dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
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status = bfin_read_SDH_E_STATUS();
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if (status & SD_CARD_DET) {
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mmc_detect_change(host->mmc, 0);
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bfin_write_SDH_E_STATUS(SD_CARD_DET);
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}
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status = bfin_read_SDH_STATUS();
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if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
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handled |= sdh_cmd_done(host, status);
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bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
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CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
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SSYNC();
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}
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status = bfin_read_SDH_STATUS();
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if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
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handled |= sdh_data_done(host, status);
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dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
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return IRQ_RETVAL(handled);
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}
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static int __devinit sdh_probe(struct platform_device *pdev)
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{
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struct mmc_host *mmc;
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struct sdh_host *host;
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struct bfin_sd_host *drv_data = get_sdh_data(pdev);
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int ret;
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if (!drv_data) {
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dev_err(&pdev->dev, "missing platform driver data\n");
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ret = -EINVAL;
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goto out;
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}
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mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
|
|
if (!mmc) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
mmc->ops = &sdh_ops;
|
|
mmc->max_segs = 32;
|
|
mmc->max_seg_size = 1 << 16;
|
|
mmc->max_blk_size = 1 << 11;
|
|
mmc->max_blk_count = 1 << 11;
|
|
mmc->max_req_size = PAGE_SIZE;
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
mmc->f_max = get_sclk();
|
|
mmc->f_min = mmc->f_max >> 9;
|
|
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
|
|
spin_lock_init(&host->lock);
|
|
host->irq = drv_data->irq_int0;
|
|
host->dma_ch = drv_data->dma_chan;
|
|
|
|
ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to request DMA channel\n");
|
|
goto out1;
|
|
}
|
|
|
|
ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to request DMA irq\n");
|
|
goto out2;
|
|
}
|
|
|
|
host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
|
|
if (host->sg_cpu == NULL) {
|
|
ret = -ENOMEM;
|
|
goto out2;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
mmc_add_host(mmc);
|
|
|
|
ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to request status irq\n");
|
|
goto out3;
|
|
}
|
|
|
|
ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to request peripheral pins\n");
|
|
goto out4;
|
|
}
|
|
#if defined(CONFIG_BF54x)
|
|
/* Secure Digital Host shares DMA with Nand controller */
|
|
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
|
|
#endif
|
|
|
|
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
|
|
SSYNC();
|
|
|
|
/* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
|
|
* mmc stack will do the detection.
|
|
*/
|
|
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
|
|
SSYNC();
|
|
|
|
return 0;
|
|
|
|
out4:
|
|
free_irq(host->irq, host);
|
|
out3:
|
|
mmc_remove_host(mmc);
|
|
dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
|
|
out2:
|
|
free_dma(host->dma_ch);
|
|
out1:
|
|
mmc_free_host(mmc);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit sdh_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (mmc) {
|
|
struct sdh_host *host = mmc_priv(mmc);
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
sdh_stop_clock(host);
|
|
free_irq(host->irq, host);
|
|
free_dma(host->dma_ch);
|
|
dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
|
|
|
|
mmc_free_host(mmc);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sdh_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
struct bfin_sd_host *drv_data = get_sdh_data(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc)
|
|
ret = mmc_suspend_host(mmc);
|
|
|
|
bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
|
|
peripheral_free_list(drv_data->pin_req);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sdh_resume(struct platform_device *dev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
struct bfin_sd_host *drv_data = get_sdh_data(dev);
|
|
int ret = 0;
|
|
|
|
ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
|
|
if (ret) {
|
|
dev_err(&dev->dev, "unable to request peripheral pins\n");
|
|
return ret;
|
|
}
|
|
|
|
bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
|
|
#if defined(CONFIG_BF54x)
|
|
/* Secure Digital Host shares DMA with Nand controller */
|
|
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
|
|
#endif
|
|
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
|
|
SSYNC();
|
|
|
|
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
|
|
SSYNC();
|
|
|
|
if (mmc)
|
|
ret = mmc_resume_host(mmc);
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
# define sdh_suspend NULL
|
|
# define sdh_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver sdh_driver = {
|
|
.probe = sdh_probe,
|
|
.remove = __devexit_p(sdh_remove),
|
|
.suspend = sdh_suspend,
|
|
.resume = sdh_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init sdh_init(void)
|
|
{
|
|
return platform_driver_register(&sdh_driver);
|
|
}
|
|
module_init(sdh_init);
|
|
|
|
static void __exit sdh_exit(void)
|
|
{
|
|
platform_driver_unregister(&sdh_driver);
|
|
}
|
|
module_exit(sdh_exit);
|
|
|
|
MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
|
|
MODULE_AUTHOR("Cliff Cai, Roy Huang");
|
|
MODULE_LICENSE("GPL");
|