717 lines
20 KiB
C
717 lines
20 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2007 Cavium Networks
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* Copyright (C) 2008 Wind River Systems
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*/
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/serial.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/string.h> /* for memset */
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#include <linux/tty.h>
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#include <linux/time.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/smp-ops.h>
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#include <asm/system.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/bootinfo.h>
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#include <asm/sections.h>
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#include <asm/time.h>
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#include <asm/octeon/octeon.h>
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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extern void cvmx_interrupt_rsl_decode(void);
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extern int __cvmx_interrupt_ecc_report_single_bit_errors;
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extern void cvmx_interrupt_rsl_enable(void);
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#endif
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extern struct plat_smp_ops octeon_smp_ops;
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#ifdef CONFIG_PCI
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extern void pci_console_init(const char *arg);
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#endif
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static unsigned long long MAX_MEMORY = 512ull << 20;
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struct octeon_boot_descriptor *octeon_boot_desc_ptr;
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struct cvmx_bootinfo *octeon_bootinfo;
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EXPORT_SYMBOL(octeon_bootinfo);
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#ifdef CONFIG_CAVIUM_RESERVE32
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uint64_t octeon_reserve32_memory;
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EXPORT_SYMBOL(octeon_reserve32_memory);
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#endif
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static int octeon_uart;
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extern asmlinkage void handle_int(void);
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extern asmlinkage void plat_irq_dispatch(void);
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/**
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* Return non zero if we are currently running in the Octeon simulator
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*
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* Returns
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*/
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int octeon_is_simulation(void)
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{
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return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
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}
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EXPORT_SYMBOL(octeon_is_simulation);
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/**
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* Return true if Octeon is in PCI Host mode. This means
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* Linux can control the PCI bus.
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*
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* Returns Non zero if Octeon in host mode.
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*/
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int octeon_is_pci_host(void)
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{
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#ifdef CONFIG_PCI
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return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
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#else
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return 0;
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#endif
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}
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/**
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* Get the clock rate of Octeon
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*
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* Returns Clock rate in HZ
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*/
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uint64_t octeon_get_clock_rate(void)
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{
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if (octeon_is_simulation())
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octeon_bootinfo->eclock_hz = 6000000;
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return octeon_bootinfo->eclock_hz;
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}
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EXPORT_SYMBOL(octeon_get_clock_rate);
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/**
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* Write to the LCD display connected to the bootbus. This display
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* exists on most Cavium evaluation boards. If it doesn't exist, then
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* this function doesn't do anything.
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*
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* @s: String to write
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*/
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void octeon_write_lcd(const char *s)
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{
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if (octeon_bootinfo->led_display_base_addr) {
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void __iomem *lcd_address =
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ioremap_nocache(octeon_bootinfo->led_display_base_addr,
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8);
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int i;
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for (i = 0; i < 8; i++, s++) {
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if (*s)
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iowrite8(*s, lcd_address + i);
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else
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iowrite8(' ', lcd_address + i);
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}
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iounmap(lcd_address);
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}
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}
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/**
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* Return the console uart passed by the bootloader
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*
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* Returns uart (0 or 1)
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*/
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int octeon_get_boot_uart(void)
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{
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int uart;
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#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
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uart = 1;
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#else
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uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
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1 : 0;
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#endif
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return uart;
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}
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/**
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* Get the coremask Linux was booted on.
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*
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* Returns Core mask
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*/
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int octeon_get_boot_coremask(void)
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{
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return octeon_boot_desc_ptr->core_mask;
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}
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/**
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* Check the hardware BIST results for a CPU
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*/
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void octeon_check_cpu_bist(void)
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{
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const int coreid = cvmx_get_core_num();
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unsigned long long mask;
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unsigned long long bist_val;
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/* Check BIST results for COP0 registers */
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mask = 0x1f00000000ull;
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bist_val = read_octeon_c0_icacheerr();
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if (bist_val & mask)
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pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
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coreid, bist_val);
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bist_val = read_octeon_c0_dcacheerr();
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if (bist_val & 1)
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pr_err("Core%d L1 Dcache parity error: "
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"CacheErr(dcache) = 0x%llx\n",
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coreid, bist_val);
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mask = 0xfc00000000000000ull;
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bist_val = read_c0_cvmmemctl();
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if (bist_val & mask)
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pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
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coreid, bist_val);
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write_octeon_c0_dcacheerr(0);
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}
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/**
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* Reboot Octeon
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*
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* @command: Command to pass to the bootloader. Currently ignored.
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*/
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static void octeon_restart(char *command)
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{
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/* Disable all watchdogs before soft reset. They don't get cleared */
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#ifdef CONFIG_SMP
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int cpu;
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for_each_online_cpu(cpu)
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cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
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#else
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cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
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#endif
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mb();
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while (1)
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cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
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}
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/**
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* Permanently stop a core.
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*
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* @arg: Ignored.
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*/
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static void octeon_kill_core(void *arg)
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{
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mb();
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if (octeon_is_simulation()) {
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/* The simulator needs the watchdog to stop for dead cores */
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cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
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/* A break instruction causes the simulator stop a core */
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asm volatile ("sync\nbreak");
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}
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}
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/**
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* Halt the system
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*/
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static void octeon_halt(void)
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{
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smp_call_function(octeon_kill_core, NULL, 0);
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switch (octeon_bootinfo->board_type) {
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case CVMX_BOARD_TYPE_NAO38:
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/* Driving a 1 to GPIO 12 shuts off this board */
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
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cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
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break;
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default:
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octeon_write_lcd("PowerOff");
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break;
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}
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octeon_kill_core(NULL);
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}
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/**
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* Handle all the error condition interrupts that might occur.
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*
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*/
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
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{
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cvmx_interrupt_rsl_decode();
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return IRQ_HANDLED;
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}
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#endif
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/**
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* Return a string representing the system type
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*
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* Returns
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*/
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const char *octeon_board_type_string(void)
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{
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static char name[80];
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sprintf(name, "%s (%s)",
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cvmx_board_type_to_string(octeon_bootinfo->board_type),
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octeon_model_get_string(read_c0_prid()));
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return name;
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}
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const char *get_system_type(void)
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__attribute__ ((alias("octeon_board_type_string")));
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void octeon_user_io_init(void)
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{
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union octeon_cvmemctl cvmmemctl;
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union cvmx_iob_fau_timeout fau_timeout;
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union cvmx_pow_nw_tim nm_tim;
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uint64_t cvmctl;
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/* Get the current settings for CP0_CVMMEMCTL_REG */
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cvmmemctl.u64 = read_c0_cvmmemctl();
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/* R/W If set, marked write-buffer entries time out the same
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* as as other entries; if clear, marked write-buffer entries
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* use the maximum timeout. */
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cvmmemctl.s.dismarkwblongto = 1;
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/* R/W If set, a merged store does not clear the write-buffer
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* entry timeout state. */
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cvmmemctl.s.dismrgclrwbto = 0;
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/* R/W Two bits that are the MSBs of the resultant CVMSEG LM
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* word location for an IOBDMA. The other 8 bits come from the
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* SCRADDR field of the IOBDMA. */
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cvmmemctl.s.iobdmascrmsb = 0;
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/* R/W If set, SYNCWS and SYNCS only order marked stores; if
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* clear, SYNCWS and SYNCS only order unmarked
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* stores. SYNCWSMARKED has no effect when DISSYNCWS is
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* set. */
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cvmmemctl.s.syncwsmarked = 0;
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/* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
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cvmmemctl.s.dissyncws = 0;
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/* R/W If set, no stall happens on write buffer full. */
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if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
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cvmmemctl.s.diswbfst = 1;
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else
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cvmmemctl.s.diswbfst = 0;
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/* R/W If set (and SX set), supervisor-level loads/stores can
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* use XKPHYS addresses with <48>==0 */
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cvmmemctl.s.xkmemenas = 0;
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/* R/W If set (and UX set), user-level loads/stores can use
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* XKPHYS addresses with VA<48>==0 */
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cvmmemctl.s.xkmemenau = 0;
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/* R/W If set (and SX set), supervisor-level loads/stores can
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* use XKPHYS addresses with VA<48>==1 */
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cvmmemctl.s.xkioenas = 0;
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/* R/W If set (and UX set), user-level loads/stores can use
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* XKPHYS addresses with VA<48>==1 */
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cvmmemctl.s.xkioenau = 0;
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/* R/W If set, all stores act as SYNCW (NOMERGE must be set
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* when this is set) RW, reset to 0. */
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cvmmemctl.s.allsyncw = 0;
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/* R/W If set, no stores merge, and all stores reach the
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* coherent bus in order. */
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cvmmemctl.s.nomerge = 0;
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/* R/W Selects the bit in the counter used for DID time-outs 0
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* = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
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* between 1x and 2x this interval. For example, with
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* DIDTTO=3, expiration interval is between 16K and 32K. */
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cvmmemctl.s.didtto = 0;
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/* R/W If set, the (mem) CSR clock never turns off. */
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cvmmemctl.s.csrckalwys = 0;
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/* R/W If set, mclk never turns off. */
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cvmmemctl.s.mclkalwys = 0;
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/* R/W Selects the bit in the counter used for write buffer
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* flush time-outs (WBFLT+11) is the bit position in an
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* internal counter used to determine expiration. The write
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* buffer expires between 1x and 2x this interval. For
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* example, with WBFLT = 0, a write buffer expires between 2K
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* and 4K cycles after the write buffer entry is allocated. */
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cvmmemctl.s.wbfltime = 0;
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/* R/W If set, do not put Istream in the L2 cache. */
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cvmmemctl.s.istrnol2 = 0;
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/* R/W The write buffer threshold. */
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cvmmemctl.s.wbthresh = 10;
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/* R/W If set, CVMSEG is available for loads/stores in
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* kernel/debug mode. */
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#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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cvmmemctl.s.cvmsegenak = 1;
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#else
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cvmmemctl.s.cvmsegenak = 0;
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#endif
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/* R/W If set, CVMSEG is available for loads/stores in
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* supervisor mode. */
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cvmmemctl.s.cvmsegenas = 0;
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/* R/W If set, CVMSEG is available for loads/stores in user
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* mode. */
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cvmmemctl.s.cvmsegenau = 0;
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/* R/W Size of local memory in cache blocks, 54 (6912 bytes)
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* is max legal value. */
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cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
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if (smp_processor_id() == 0)
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pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
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write_c0_cvmmemctl(cvmmemctl.u64);
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/* Move the performance counter interrupts to IRQ 6 */
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cvmctl = read_c0_cvmctl();
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cvmctl &= ~(7 << 7);
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cvmctl |= 6 << 7;
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write_c0_cvmctl(cvmctl);
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/* Set a default for the hardware timeouts */
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fau_timeout.u64 = 0;
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fau_timeout.s.tout_val = 0xfff;
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/* Disable tagwait FAU timeout */
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fau_timeout.s.tout_enb = 0;
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cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
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nm_tim.u64 = 0;
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/* 4096 cycles */
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nm_tim.s.nw_tim = 3;
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cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
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write_octeon_c0_icacheerr(0);
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write_c0_derraddr1(0);
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}
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/**
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* Early entry point for arch setup
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*/
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void __init prom_init(void)
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{
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struct cvmx_sysinfo *sysinfo;
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const int coreid = cvmx_get_core_num();
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int i;
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int argc;
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#ifdef CONFIG_CAVIUM_RESERVE32
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int64_t addr = -1;
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#endif
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/*
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* The bootloader passes a pointer to the boot descriptor in
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* $a3, this is available as fw_arg3.
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*/
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octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
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octeon_bootinfo =
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cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
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cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
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/*
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* Only enable the LED controller if we're running on a CN38XX, CN58XX,
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* or CN56XX. The CN30XX and CN31XX don't have an LED controller.
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*/
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if (!octeon_is_simulation() &&
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octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
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cvmx_write_csr(CVMX_LED_EN, 0);
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cvmx_write_csr(CVMX_LED_PRT, 0);
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cvmx_write_csr(CVMX_LED_DBG, 0);
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cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
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cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
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cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
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cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
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cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
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cvmx_write_csr(CVMX_LED_EN, 1);
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}
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#ifdef CONFIG_CAVIUM_RESERVE32
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/*
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* We need to temporarily allocate all memory in the reserve32
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* region. This makes sure the kernel doesn't allocate this
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* memory when it is getting memory from the
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* bootloader. Later, after the memory allocations are
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* complete, the reserve32 will be freed.
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*
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* Allocate memory for RESERVED32 aligned on 2MB boundary. This
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* is in case we later use hugetlb entries with it.
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*/
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addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
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0, 0, 2 << 20,
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"CAVIUM_RESERVE32", 0);
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if (addr < 0)
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pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
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else
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octeon_reserve32_memory = addr;
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#endif
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#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
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if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
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pr_info("Skipping L2 locking due to reduced L2 cache size\n");
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} else {
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uint32_t ebase = read_c0_ebase() & 0x3ffff000;
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#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
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/* TLB refill */
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cvmx_l2c_lock_mem_region(ebase, 0x100);
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#endif
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#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
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/* General exception */
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cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
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#endif
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#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
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/* Interrupt handler */
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cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
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#endif
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#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
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cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
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cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
|
|
cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
sysinfo = cvmx_sysinfo_get();
|
|
memset(sysinfo, 0, sizeof(*sysinfo));
|
|
sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
|
|
sysinfo->phy_mem_desc_ptr =
|
|
cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
|
|
sysinfo->core_mask = octeon_bootinfo->core_mask;
|
|
sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
|
|
sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
|
|
sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
|
|
sysinfo->board_type = octeon_bootinfo->board_type;
|
|
sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
|
|
sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
|
|
memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
|
|
sizeof(sysinfo->mac_addr_base));
|
|
sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
|
|
memcpy(sysinfo->board_serial_number,
|
|
octeon_bootinfo->board_serial_number,
|
|
sizeof(sysinfo->board_serial_number));
|
|
sysinfo->compact_flash_common_base_addr =
|
|
octeon_bootinfo->compact_flash_common_base_addr;
|
|
sysinfo->compact_flash_attribute_base_addr =
|
|
octeon_bootinfo->compact_flash_attribute_base_addr;
|
|
sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
|
|
sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
|
|
sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
|
|
|
|
|
|
octeon_check_cpu_bist();
|
|
|
|
octeon_uart = octeon_get_boot_uart();
|
|
|
|
/*
|
|
* Disable All CIU Interrupts. The ones we need will be
|
|
* enabled later. Read the SUM register so we know the write
|
|
* completed.
|
|
*/
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
|
|
cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
|
|
cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
|
|
|
|
#ifdef CONFIG_SMP
|
|
octeon_write_lcd("LinuxSMP");
|
|
#else
|
|
octeon_write_lcd("Linux");
|
|
#endif
|
|
|
|
#ifdef CONFIG_CAVIUM_GDB
|
|
/*
|
|
* When debugging the linux kernel, force the cores to enter
|
|
* the debug exception handler to break in.
|
|
*/
|
|
if (octeon_get_boot_debug_flag()) {
|
|
cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
|
|
cvmx_read_csr(CVMX_CIU_DINT);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* BIST should always be enabled when doing a soft reset. L2
|
|
* Cache locking for instance is not cleared unless BIST is
|
|
* enabled. Unfortunately due to a chip errata G-200 for
|
|
* Cn38XX and CN31XX, BIST msut be disabled on these parts.
|
|
*/
|
|
if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
|
|
OCTEON_IS_MODEL(OCTEON_CN31XX))
|
|
cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
|
|
else
|
|
cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
|
|
|
|
/* Default to 64MB in the simulator to speed things up */
|
|
if (octeon_is_simulation())
|
|
MAX_MEMORY = 64ull << 20;
|
|
|
|
arcs_cmdline[0] = 0;
|
|
argc = octeon_boot_desc_ptr->argc;
|
|
for (i = 0; i < argc; i++) {
|
|
const char *arg =
|
|
cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
|
|
if ((strncmp(arg, "MEM=", 4) == 0) ||
|
|
(strncmp(arg, "mem=", 4) == 0)) {
|
|
sscanf(arg + 4, "%llu", &MAX_MEMORY);
|
|
MAX_MEMORY <<= 20;
|
|
if (MAX_MEMORY == 0)
|
|
MAX_MEMORY = 32ull << 30;
|
|
} else if (strcmp(arg, "ecc_verbose") == 0) {
|
|
#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
|
|
__cvmx_interrupt_ecc_report_single_bit_errors = 1;
|
|
pr_notice("Reporting of single bit ECC errors is "
|
|
"turned on\n");
|
|
#endif
|
|
} else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
|
|
sizeof(arcs_cmdline) - 1) {
|
|
strcat(arcs_cmdline, " ");
|
|
strcat(arcs_cmdline, arg);
|
|
}
|
|
}
|
|
|
|
if (strstr(arcs_cmdline, "console=") == NULL) {
|
|
#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
|
|
strcat(arcs_cmdline, " console=ttyS0,115200");
|
|
#else
|
|
if (octeon_uart == 1)
|
|
strcat(arcs_cmdline, " console=ttyS1,115200");
|
|
else
|
|
strcat(arcs_cmdline, " console=ttyS0,115200");
|
|
#endif
|
|
}
|
|
|
|
if (octeon_is_simulation()) {
|
|
/*
|
|
* The simulator uses a mtdram device pre filled with
|
|
* the filesystem. Also specify the calibration delay
|
|
* to avoid calculating it every time.
|
|
*/
|
|
strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
|
|
}
|
|
|
|
mips_hpt_frequency = octeon_get_clock_rate();
|
|
|
|
octeon_init_cvmcount();
|
|
octeon_setup_delays();
|
|
|
|
_machine_restart = octeon_restart;
|
|
_machine_halt = octeon_halt;
|
|
|
|
octeon_user_io_init();
|
|
register_smp_ops(&octeon_smp_ops);
|
|
}
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
uint64_t mem_alloc_size;
|
|
uint64_t total;
|
|
int64_t memory;
|
|
|
|
total = 0;
|
|
|
|
/* First add the init memory we will be returning. */
|
|
memory = __pa_symbol(&__init_begin) & PAGE_MASK;
|
|
mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
|
|
if (mem_alloc_size > 0) {
|
|
add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
|
|
total += mem_alloc_size;
|
|
}
|
|
|
|
/*
|
|
* The Mips memory init uses the first memory location for
|
|
* some memory vectors. When SPARSEMEM is in use, it doesn't
|
|
* verify that the size is big enough for the final
|
|
* vectors. Making the smallest chuck 4MB seems to be enough
|
|
* to consistantly work.
|
|
*/
|
|
mem_alloc_size = 4 << 20;
|
|
if (mem_alloc_size > MAX_MEMORY)
|
|
mem_alloc_size = MAX_MEMORY;
|
|
|
|
/*
|
|
* When allocating memory, we want incrementing addresses from
|
|
* bootmem_alloc so the code in add_memory_region can merge
|
|
* regions next to each other.
|
|
*/
|
|
cvmx_bootmem_lock();
|
|
while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
|
|
&& (total < MAX_MEMORY)) {
|
|
#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
|
|
memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
|
|
__pa_symbol(&__init_end), -1,
|
|
0x100000,
|
|
CVMX_BOOTMEM_FLAG_NO_LOCKING);
|
|
#elif defined(CONFIG_HIGHMEM)
|
|
memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
|
|
0x100000,
|
|
CVMX_BOOTMEM_FLAG_NO_LOCKING);
|
|
#else
|
|
memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
|
|
0x100000,
|
|
CVMX_BOOTMEM_FLAG_NO_LOCKING);
|
|
#endif
|
|
if (memory >= 0) {
|
|
/*
|
|
* This function automatically merges address
|
|
* regions next to each other if they are
|
|
* received in incrementing order.
|
|
*/
|
|
add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
|
|
total += mem_alloc_size;
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
cvmx_bootmem_unlock();
|
|
|
|
#ifdef CONFIG_CAVIUM_RESERVE32
|
|
/*
|
|
* Now that we've allocated the kernel memory it is safe to
|
|
* free the reserved region. We free it here so that builtin
|
|
* drivers can use the memory.
|
|
*/
|
|
if (octeon_reserve32_memory)
|
|
cvmx_bootmem_free_named("CAVIUM_RESERVE32");
|
|
#endif /* CONFIG_CAVIUM_RESERVE32 */
|
|
|
|
if (total == 0)
|
|
panic("Unable to allocate memory from "
|
|
"cvmx_bootmem_phy_alloc\n");
|
|
}
|
|
|
|
|
|
int prom_putchar(char c)
|
|
{
|
|
uint64_t lsrval;
|
|
|
|
/* Spin until there is room */
|
|
do {
|
|
lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
|
|
} while ((lsrval & 0x20) == 0);
|
|
|
|
/* Write the byte */
|
|
cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
|
|
return 1;
|
|
}
|
|
|
|
void prom_free_prom_memory(void)
|
|
{
|
|
#ifdef CONFIG_CAVIUM_DECODE_RSL
|
|
cvmx_interrupt_rsl_enable();
|
|
|
|
/* Add an interrupt handler for general failures. */
|
|
if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
|
|
"RML/RSL", octeon_rlm_interrupt)) {
|
|
panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
|
|
}
|
|
#endif
|
|
}
|