157 lines
4.1 KiB
C
157 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright 2014 Cisco Systems, Inc. All rights reserved. */
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#ifndef _VNIC_WQ_H_
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#define _VNIC_WQ_H_
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#include <linux/pci.h>
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#include "vnic_dev.h"
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#include "vnic_cq.h"
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/* Work queue control */
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struct vnic_wq_ctrl {
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u64 ring_base; /* 0x00 */
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u32 ring_size; /* 0x08 */
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u32 pad0;
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u32 posted_index; /* 0x10 */
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u32 pad1;
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u32 cq_index; /* 0x18 */
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u32 pad2;
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u32 enable; /* 0x20 */
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u32 pad3;
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u32 running; /* 0x28 */
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u32 pad4;
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u32 fetch_index; /* 0x30 */
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u32 pad5;
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u32 dca_value; /* 0x38 */
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u32 pad6;
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u32 error_interrupt_enable; /* 0x40 */
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u32 pad7;
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u32 error_interrupt_offset; /* 0x48 */
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u32 pad8;
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u32 error_status; /* 0x50 */
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u32 pad9;
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};
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struct vnic_wq_buf {
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struct vnic_wq_buf *next;
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dma_addr_t dma_addr;
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void *os_buf;
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unsigned int len;
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unsigned int index;
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int sop;
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void *desc;
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};
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/* Break the vnic_wq_buf allocations into blocks of 64 entries */
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#define VNIC_WQ_BUF_MIN_BLK_ENTRIES 32
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#define VNIC_WQ_BUF_DFLT_BLK_ENTRIES 64
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#define VNIC_WQ_BUF_BLK_ENTRIES(entries) \
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((unsigned int)(entries < VNIC_WQ_BUF_DFLT_BLK_ENTRIES) ? \
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VNIC_WQ_BUF_MIN_BLK_ENTRIES : VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
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#define VNIC_WQ_BUF_BLK_SZ \
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(VNIC_WQ_BUF_DFLT_BLK_ENTRIES * sizeof(struct vnic_wq_buf))
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#define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
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DIV_ROUND_UP(entries, VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
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#define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
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DIV_ROUND_UP(entries, VNIC_WQ_BUF_DFLT_BLK_ENTRIES)
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#define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
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struct vnic_wq {
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unsigned int index;
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struct vnic_dev *vdev;
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struct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */
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struct vnic_dev_ring ring;
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struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
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struct vnic_wq_buf *to_use;
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struct vnic_wq_buf *to_clean;
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unsigned int pkts_outstanding;
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};
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static inline unsigned int svnic_wq_desc_avail(struct vnic_wq *wq)
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{
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/* how many does SW own? */
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return wq->ring.desc_avail;
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}
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static inline unsigned int svnic_wq_desc_used(struct vnic_wq *wq)
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{
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/* how many does HW own? */
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return wq->ring.desc_count - wq->ring.desc_avail - 1;
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}
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static inline void *svnic_wq_next_desc(struct vnic_wq *wq)
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{
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return wq->to_use->desc;
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}
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static inline void svnic_wq_post(struct vnic_wq *wq,
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void *os_buf, dma_addr_t dma_addr,
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unsigned int len, int sop, int eop)
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{
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struct vnic_wq_buf *buf = wq->to_use;
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buf->sop = sop;
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buf->os_buf = eop ? os_buf : NULL;
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buf->dma_addr = dma_addr;
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buf->len = len;
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buf = buf->next;
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if (eop) {
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/* Adding write memory barrier prevents compiler and/or CPU
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* reordering, thus avoiding descriptor posting before
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* descriptor is initialized. Otherwise, hardware can read
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* stale descriptor fields.
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*/
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wmb();
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iowrite32(buf->index, &wq->ctrl->posted_index);
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}
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wq->to_use = buf;
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wq->ring.desc_avail--;
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}
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static inline void svnic_wq_service(struct vnic_wq *wq,
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struct cq_desc *cq_desc, u16 completed_index,
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void (*buf_service)(struct vnic_wq *wq,
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struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
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void *opaque)
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{
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struct vnic_wq_buf *buf;
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buf = wq->to_clean;
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while (1) {
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(*buf_service)(wq, cq_desc, buf, opaque);
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wq->ring.desc_avail++;
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wq->to_clean = buf->next;
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if (buf->index == completed_index)
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break;
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buf = wq->to_clean;
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}
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}
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void svnic_wq_free(struct vnic_wq *wq);
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int svnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
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unsigned int index, unsigned int desc_count, unsigned int desc_size);
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int vnic_wq_devcmd2_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
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unsigned int desc_count, unsigned int desc_size);
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void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
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unsigned int fetch_index, unsigned int post_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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void svnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
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unsigned int error_interrupt_enable,
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unsigned int error_interrupt_offset);
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unsigned int svnic_wq_error_status(struct vnic_wq *wq);
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void svnic_wq_enable(struct vnic_wq *wq);
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int svnic_wq_disable(struct vnic_wq *wq);
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void svnic_wq_clean(struct vnic_wq *wq,
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void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
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#endif /* _VNIC_WQ_H_ */
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